/*
 * Hardware Sprite Test Fixture
 *
 * by Brendan Doms, Sean McBride, Brian Shih, and Mikell Taylor
 * 		(Olin College - Computer Architecture - Fall 2005)
 * 
 */

`include "fpga_top.v"

module TEST;
	parameter ClockDelay = 20;
	
	reg clk;
	
	initial clk = 0;
	always #(ClockDelay/2) clk = ~clk;

	reg Reset, button1, button2;
	wire R, G, B, HSync, VSync;
	
	initial	// Stimulus
	begin
		Reset = 1;
		button1=0;
		button2=0;
		#(ClockDelay);
		Reset = 0;
	end
	
	FPGA UUT (clk, Reset, button1, button2, R, G, B, HSync, VSync);
	
	initial // Response
		$monitor($time, "	%b %b %b %b &b", R, G, B, HSync, VSync);
	
endmodule