`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Olin College
// Engineer: Kevin Sihlanick Dan Cody Boris Dieseldorf
// 
// Create Date:    17:02:42 12/09/2007 
// Design Name: FPGA based NTSC video, might play games
// Module Name:    cafinal 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module cafinal(o_leds, trigger, signal, clk, reset, address, din);
    output [7:0] signal;
	 output [7:0] o_leds;
	 output trigger;
    input clk;
    input reset;
	 output [23:0] address;
	 input [15:0] din;
	 
	 assign address = 0;
	 
	reg [31:0] count;
	
	//assign o_leds = count[31:24];
	
	assign o_leds = din[7:0];
	
	always @(posedge clk or posedge reset)
	begin
		if(reset) count <= 32'h0;
		else count <=count + 1'b1;
		
	end
	
	NTSC dan(signal, trigger, clk);
	
endmodule