Model { Name "mux" Version 6.5 MdlSubVersion 0 GraphicalInterface { NumRootInports 34 Inport { Name "SelectCode/5" } Inport { Name "In0" } Inport { Name "In1" } Inport { Name "In2" } Inport { Name "In3" } Inport { Name "In4" } Inport { Name "In5" } Inport { Name "In6" } Inport { Name "In7" } Inport { Name "In8" } Inport { Name "In9" } Inport { Name "In10" } Inport { Name "In11" } Inport { Name "In12" } Inport { Name "In13" } Inport { Name "In14" } Inport { Name "In15" } Inport { Name "In16" } Inport { Name "In17" } Inport { Name "In18" } Inport { Name "In19" } Inport { Name "In20" } Inport { Name "In21" } Inport { Name "In22" } Inport { Name "In23" } Inport { Name "In24" } Inport { Name "In25" } Inport { Name "In26" } Inport { Name "In27" } Inport { Name "In28" } Inport { Name "In29" } Inport { Name "In30" } Inport { Name "In31" } Inport { Name "Start" } NumRootOutports 2 Outport { BusObject "" BusOutputAsStruct "off" Name "Output" } Outport { BusObject "" BusOutputAsStruct "off" Name "Done" } ParameterArgumentNames "" ComputedModelVersion "1.24" NumModelReferences 0 NumTestPointedSignals 0 } SavedCharacterEncoding "windows-1252" SaveDefaultBlockParams on SampleTimeColors off LibraryLinkDisplay "none" WideLines off ShowLineDimensions off ShowPortDataTypes off ShowLoopsOnError on IgnoreBidirectionalLines off ShowStorageClass off ShowTestPointIcons on ShowViewerIcons on SortedOrder off ExecutionContextIcon off ShowLinearizationAnnotations on ScopeRefreshTime 0.035000 OverrideScopeRefreshTime on DisableAllScopes off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" MinMaxOverflowArchiveMode "Overwrite" BlockNameDataTip off BlockParametersDataTip off BlockDescriptionStringDataTip off ToolBar on StatusBar on BrowserShowLibraryLinks off BrowserLookUnderMasks off Created "Fri Dec 05 21:01:12 2008" Creator "pchung" UpdateHistory "UpdateHistoryNever" ModifiedByFormat "%" LastModifiedBy "cma" ModifiedDateFormat "%" LastModifiedDate "Sat Dec 13 19:28:08 2008" ModelVersionFormat "1.%" ConfigurationManager "None" LinearizationMsg "none" Profile off ParamWorkspaceSource "MATLABWorkspace" AccelSystemTargetFile "accel.tlc" AccelTemplateMakefile "accel_default_tmf" AccelMakeCommand "make_rtw" TryForcingSFcnDF off RecordCoverage off CovPath "/" CovSaveName "covdata" CovMetricSettings "dw" CovNameIncrementing off CovHtmlReporting on covSaveCumulativeToWorkspaceVar on CovSaveSingleToWorkspaceVar on CovCumulativeVarName "covCumulativeData" CovCumulativeReport off CovReportOnPause on ExtModeBatchMode off ExtModeEnableFloating on ExtModeTrigType "manual" ExtModeTrigMode "normal" ExtModeTrigPort "1" ExtModeTrigElement "any" ExtModeTrigDuration 1000 ExtModeTrigDurationFloating "auto" ExtModeTrigHoldOff 0 ExtModeTrigDelay 0 ExtModeTrigDirection "rising" ExtModeTrigLevel 0 ExtModeArchiveMode "off" ExtModeAutoIncOneShot off ExtModeIncDirWhenArm off ExtModeAddSuffixToVar off ExtModeWriteAllDataToWs off ExtModeArmWhenConnect on ExtModeSkipDownloadWhenConnect off ExtModeLogAll on ExtModeAutoUpdateStatusClock on BufferReuse on ProdHWDeviceType "32-bit Generic" ShowModelReferenceBlockVersion off ShowModelReferenceBlockIO off Array { Type "Handle" Dimension 1 Simulink.ConfigSet { $ObjectID 1 Version "1.2.0" Array { Type "Handle" Dimension 7 Simulink.SolverCC { $ObjectID 2 Version "1.2.0" StartTime "0.0" StopTime "10.0" AbsTol "auto" FixedStep "auto" InitialStep "auto" MaxNumMinSteps "-1" MaxOrder 5 ConsecutiveZCsStepRelTol "10*128*eps" MaxConsecutiveZCs "1000" ExtrapolationOrder 4 NumberNewtonIterations 1 MaxStep "auto" MinStep "auto" MaxConsecutiveMinStep "1" RelTol "1e-3" SolverMode "Auto" Solver "ode45" SolverName "ode45" ZeroCrossControl "UseLocalSettings" AlgebraicLoopSolver "TrustRegion" SolverResetMethod "Fast" PositivePriorityOrder off AutoInsertRateTranBlk off SampleTimeConstraint "Unconstrained" RateTranMode "Deterministic" } Simulink.DataIOCC { $ObjectID 3 Version "1.2.0" Decimation "1" ExternalInput "[t, u]" FinalStateName "xFinal" InitialState "xInitial" LimitDataPoints on MaxDataPoints "1000" LoadExternalInput off LoadInitialState off SaveFinalState off SaveFormat "Array" SaveOutput on SaveState off SignalLogging on InspectSignalLogs off SaveTime on StateSaveName "xout" TimeSaveName "tout" OutputSaveName "yout" SignalLoggingName "logsout" OutputOption "RefineOutputTimes" OutputTimes "[]" Refine "1" } Simulink.OptimizationCC { $ObjectID 4 Array { Type "Cell" Dimension 5 Cell "ZeroExternalMemoryAtStartup" Cell "ZeroInternalMemoryAtStartup" Cell "InitFltsAndDblsToZero" Cell "OptimizeModelRefInitCode" Cell "NoFixptDivByZeroProtection" PropName "DisabledProps" } Version "1.2.0" BlockReduction on BooleanDataType on ConditionallyExecuteInputs on InlineParams off InlineInvariantSignals off OptimizeBlockIOStorage on BufferReuse on EnforceIntegerDowncast on ExpressionFolding on FoldNonRolledExpr on LocalBlockOutputs on ParameterPooling on RollThreshold 5 SystemCodeInlineAuto off StateBitsets off DataBitsets off UseTempVars off ZeroExternalMemoryAtStartup on ZeroInternalMemoryAtStartup on InitFltsAndDblsToZero on NoFixptDivByZeroProtection off EfficientFloat2IntCast off OptimizeModelRefInitCode off LifeSpan "inf" BufferReusableBoundary on } Simulink.DebuggingCC { $ObjectID 5 Version "1.2.0" RTPrefix "error" ConsistencyChecking "none" ArrayBoundsChecking "none" SignalInfNanChecking "none" ReadBeforeWriteMsg "UseLocalSettings" WriteAfterWriteMsg "UseLocalSettings" WriteAfterReadMsg "UseLocalSettings" AlgebraicLoopMsg "warning" ArtificialAlgebraicLoopMsg "warning" CheckSSInitialOutputMsg on CheckExecutionContextPreStartOutputMsg off CheckExecutionContextRuntimeOutputMsg off SignalResolutionControl "UseLocalSettings" BlockPriorityViolationMsg "warning" MinStepSizeMsg "warning" TimeAdjustmentMsg "none" MaxConsecutiveZCsMsg "error" SolverPrmCheckMsg "warning" InheritedTsInSrcMsg "warning" DiscreteInheritContinuousMsg "warning" MultiTaskDSMMsg "error" MultiTaskCondExecSysMsg "error" MultiTaskRateTransMsg "error" SingleTaskRateTransMsg "none" TasksWithSamePriorityMsg "warning" SigSpecEnsureSampleTimeMsg "warning" CheckMatrixSingularityMsg "none" IntegerOverflowMsg "warning" Int32ToFloatConvMsg "warning" ParameterDowncastMsg "error" ParameterOverflowMsg "error" ParameterUnderflowMsg "none" ParameterPrecisionLossMsg "warning" UnderSpecifiedDataTypeMsg "none" UnnecessaryDatatypeConvMsg "none" VectorMatrixConversionMsg "none" InvalidFcnCallConnMsg "error" FcnCallInpInsideContextMsg "Use local settings" SignalLabelMismatchMsg "none" UnconnectedInputMsg "warning" UnconnectedOutputMsg "warning" UnconnectedLineMsg "warning" SFcnCompatibilityMsg "none" UniqueDataStoreMsg "none" BusObjectLabelMismatch "warning" RootOutportRequireBusObject "warning" AssertControl "UseLocalSettings" EnableOverflowDetection off ModelReferenceIOMsg "none" ModelReferenceVersionMismatchMessage "none" ModelReferenceIOMismatchMessage "none" ModelReferenceCSMismatchMessage "none" ModelReferenceSimTargetVerbose off UnknownTsInhSupMsg "warning" ModelReferenceDataLoggingMessage "warning" ModelReferenceSymbolNameMessage "warning" ModelReferenceExtraNoncontSigs "error" StrictBusMsg "Warning" } Simulink.HardwareCC { $ObjectID 6 Version "1.2.0" ProdBitPerChar 8 ProdBitPerShort 16 ProdBitPerInt 32 ProdBitPerLong 32 ProdIntDivRoundTo "Undefined" ProdEndianess "Unspecified" ProdWordSize 32 ProdShiftRightIntArith on ProdHWDeviceType "32-bit Generic" TargetBitPerChar 8 TargetBitPerShort 16 TargetBitPerInt 32 TargetBitPerLong 32 TargetShiftRightIntArith on TargetIntDivRoundTo "Undefined" TargetEndianess "Unspecified" TargetWordSize 32 TargetTypeEmulationWarnSuppressLevel 0 TargetPreprocMaxBitsSint 32 TargetPreprocMaxBitsUint 32 TargetHWDeviceType "Specified" TargetUnknown off ProdEqTarget on } Simulink.ModelReferenceCC { $ObjectID 7 Version "1.2.0" UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange" CheckModelReferenceTargetMessage "error" ModelReferenceNumInstancesAllowed "Multi" ModelReferencePassRootInputsByReference on ModelReferenceMinAlgLoopOccurrences off } Simulink.RTWCC { $BackupClass "Simulink.RTWCC" $ObjectID 8 Array { Type "Cell" Dimension 1 Cell "IncludeHyperlinkInReport" PropName "DisabledProps" } Version "1.2.0" SystemTargetFile "grt.tlc" GenCodeOnly off MakeCommand "make_rtw" GenerateMakefile on TemplateMakefile "grt_default_tmf" GenerateReport off SaveLog off RTWVerbose on RetainRTWFile off ProfileTLC off TLCDebug off TLCCoverage off TLCAssert off ProcessScriptMode "Default" ConfigurationMode "Optimized" ConfigAtBuild off IncludeHyperlinkInReport off LaunchReport off TargetLang "C" IncludeBusHierarchyInRTWFileBlockHierarchyMap off IncludeERTFirstTime off Array { Type "Handle" Dimension 2 Simulink.CodeAppCC { $ObjectID 9 Array { Type "Cell" Dimension 16 Cell "IgnoreCustomStorageClasses" Cell "InsertBlockDesc" Cell "SFDataObjDesc" Cell "SimulinkDataObjDesc" Cell "DefineNamingRule" Cell "SignalNamingRule" Cell "ParamNamingRule" Cell "InlinedPrmAccess" Cell "CustomSymbolStr" Cell "CustomSymbolStrGlobalVar" Cell "CustomSymbolStrType" Cell "CustomSymbolStrField" Cell "CustomSymbolStrFcn" Cell "CustomSymbolStrBlkIO" Cell "CustomSymbolStrTmpVar" Cell "CustomSymbolStrMacro" PropName "DisabledProps" } Version "1.2.0" ForceParamTrailComments off GenerateComments on IgnoreCustomStorageClasses on IncHierarchyInIds off MaxIdLength 31 PreserveName off PreserveNameWithParent off ShowEliminatedStatement off IncAutoGenComments off SimulinkDataObjDesc off SFDataObjDesc off IncDataTypeInIds off PrefixModelToSubsysFcnNames on MangleLength 1 CustomSymbolStrGlobalVar "$R$N$M" CustomSymbolStrType "$N$R$M" CustomSymbolStrField "$N$M" CustomSymbolStrFcn "$R$N$M$F" CustomSymbolStrBlkIO "rtb_$N$M" CustomSymbolStrTmpVar "$N$M" CustomSymbolStrMacro "$R$N$M" DefineNamingRule "None" ParamNamingRule "None" SignalNamingRule "None" InsertBlockDesc off SimulinkBlockComments on EnableCustomComments off InlinedPrmAccess "Literals" ReqsInCode off } Simulink.GRTTargetCC { $BackupClass "Simulink.TargetCC" $ObjectID 10 Array { Type "Cell" Dimension 15 Cell "IncludeMdlTerminateFcn" Cell "CombineOutputUpdateFcns" Cell "SuppressErrorStatus" Cell "ERTCustomFileBanners" Cell "GenerateSampleERTMain" Cell "GenerateTestInterfaces" Cell "ModelStepFunctionPrototypeControlComp" "liant" Cell "MultiInstanceERTCode" Cell "PurelyIntegerCode" Cell "SupportNonFinite" Cell "SupportComplex" Cell "SupportAbsoluteTime" Cell "SupportContinuousTime" Cell "SupportNonInlinedSFcns" Cell "PortableWordSizes" PropName "DisabledProps" } Version "1.2.0" TargetFcnLib "ansi_tfl_tmw.mat" TargetLibSuffix "" TargetPreCompLibLocation "" GenFloatMathFcnCalls "ANSI_C" UtilityFuncGeneration "Auto" GenerateFullHeader on GenerateSampleERTMain off GenerateTestInterfaces off IsPILTarget off ModelReferenceCompliant on IncludeMdlTerminateFcn on CombineOutputUpdateFcns off SuppressErrorStatus off IncludeFileDelimiter "Auto" ERTCustomFileBanners off SupportAbsoluteTime on LogVarNameModifier "rt_" MatFileLogging on MultiInstanceERTCode off SupportNonFinite on SupportComplex on PurelyIntegerCode off SupportContinuousTime on SupportNonInlinedSFcns on EnableShiftOperators on ParenthesesLevel "Nominal" ExtMode off ExtModeStaticAlloc off ExtModeTesting off ExtModeStaticAllocSize 1000000 ExtModeTransport 0 ExtModeMexFile "ext_comm" RTWCAPISignals off RTWCAPIParams off RTWCAPIStates off GenerateASAP2 off } PropName "Components" } } PropName "Components" } Name "Configuration" SimulationMode "normal" CurrentDlgPage "Solver" } PropName "ConfigurationSets" } Simulink.ConfigSet { $PropName "ActiveConfigurationSet" $ObjectID 1 } BlockDefaults { Orientation "right" ForegroundColor "black" BackgroundColor "white" DropShadow off NamePlacement "normal" FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" ShowName on } BlockParameterDefaults { Block { BlockType DataTypeConversion OutDataTypeMode "Inherit via back propagation" OutDataType "sfix(16)" OutScaling "2^0" LockScale off ConvertRealWorld "Real World Value (RWV)" RndMeth "Zero" SaturateOnIntegerOverflow on SampleTime "-1" } Block { BlockType Demux Outputs "4" DisplayOption "none" BusSelectionMode off } Block { BlockType Inport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" LatchByDelayingOutsideSignal off LatchByCopyingInsideSignal off Interpolate on } Block { BlockType Logic Operator "AND" Inputs "2" IconShape "rectangular" AllPortsSameDT on OutDataTypeMode "Logical (see Configuration Parameters: Optimiza" "tion)" LogicDataType "uint(8)" SampleTime "-1" } Block { BlockType Outport Port "1" UseBusObject off BusObject "BusObject" BusOutputAsStruct off PortDimensions "-1" SampleTime "-1" DataType "auto" OutDataType "sfix(16)" OutScaling "2^0" SignalType "auto" SamplingMode "auto" OutputWhenDisabled "held" InitialOutput "[]" } Block { BlockType Reference } Block { BlockType SubSystem ShowPortLabels on Permissions "ReadWrite" PermitHierarchicalResolution "All" TreatAsAtomicUnit off SystemSampleTime "-1" RTWFcnNameOpts "Auto" RTWFileNameOpts "Auto" RTWMemSecFuncInitTerm "Inherit from model" RTWMemSecFuncExecute "Inherit from model" RTWMemSecDataConstants "Inherit from model" RTWMemSecDataInternal "Inherit from model" RTWMemSecDataParameters "Inherit from model" SimViewingDevice off DataTypeOverride "UseLocalSettings" MinMaxOverflowLogging "UseLocalSettings" } } AnnotationDefaults { HorizontalAlignment "center" VerticalAlignment "middle" ForegroundColor "black" BackgroundColor "white" DropShadow off FontName "Arial" FontSize 10 FontWeight "normal" FontAngle "normal" } LineDefaults { FontName "Arial" FontSize 9 FontWeight "normal" FontAngle "normal" } System { Name "mux" Location [2, 88, 1411, 841] Open on ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" ReportName "simulink-default.rpt" Block { BlockType Inport Name "SelectCode/5" Position [483, 35, 497, 65] Orientation "down" NamePlacement "alternate" IconDisplay "Port number" PortDimensions "5" } Block { BlockType Inport Name "In0" Position [45, 233, 75, 247] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "In1" Position [45, 298, 75, 312] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "In2" Position [45, 358, 75, 372] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "In3" Position [45, 423, 75, 437] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "In4" Position [45, 483, 75, 497] Port "6" IconDisplay "Port number" } Block { BlockType Inport Name "In5" Position [45, 548, 75, 562] Port "7" IconDisplay "Port number" } Block { BlockType Inport Name "In6" Position [45, 613, 75, 627] Port "8" IconDisplay "Port number" } Block { BlockType Inport Name "In7" Position [45, 678, 75, 692] Port "9" IconDisplay "Port number" } Block { BlockType Inport Name "In8" Position [45, 743, 75, 757] Port "10" IconDisplay "Port number" } Block { BlockType Inport Name "In9" Position [45, 808, 75, 822] Port "11" IconDisplay "Port number" } Block { BlockType Inport Name "In10" Position [45, 873, 75, 887] Port "12" IconDisplay "Port number" } Block { BlockType Inport Name "In11" Position [45, 938, 75, 952] Port "13" IconDisplay "Port number" } Block { BlockType Inport Name "In12" Position [45, 1003, 75, 1017] Port "14" IconDisplay "Port number" } Block { BlockType Inport Name "In13" Position [45, 1068, 75, 1082] Port "15" IconDisplay "Port number" } Block { BlockType Inport Name "In14" Position [45, 1138, 75, 1152] Port "16" IconDisplay "Port number" } Block { BlockType Inport Name "In15" Position [45, 1203, 75, 1217] Port "17" IconDisplay "Port number" } Block { BlockType Inport Name "In16" Position [45, 1268, 75, 1282] Port "18" IconDisplay "Port number" } Block { BlockType Inport Name "In17" Position [45, 1333, 75, 1347] Port "19" IconDisplay "Port number" } Block { BlockType Inport Name "In18" Position [45, 1398, 75, 1412] Port "20" IconDisplay "Port number" } Block { BlockType Inport Name "In19" Position [45, 1463, 75, 1477] Port "21" IconDisplay "Port number" } Block { BlockType Inport Name "In20" Position [45, 1528, 75, 1542] Port "22" IconDisplay "Port number" } Block { BlockType Inport Name "In21" Position [45, 1593, 75, 1607] Port "23" IconDisplay "Port number" } Block { BlockType Inport Name "In22" Position [45, 1658, 75, 1672] Port "24" IconDisplay "Port number" } Block { BlockType Inport Name "In23" Position [45, 1723, 75, 1737] Port "25" IconDisplay "Port number" } Block { BlockType Inport Name "In24" Position [45, 1788, 75, 1802] Port "26" IconDisplay "Port number" } Block { BlockType Inport Name "In25" Position [45, 1858, 75, 1872] Port "27" IconDisplay "Port number" } Block { BlockType Inport Name "In26" Position [45, 1923, 75, 1937] Port "28" IconDisplay "Port number" } Block { BlockType Inport Name "In27" Position [45, 1988, 75, 2002] Port "29" IconDisplay "Port number" } Block { BlockType Inport Name "In28" Position [45, 2053, 75, 2067] Port "30" IconDisplay "Port number" } Block { BlockType Inport Name "In29" Position [45, 2118, 75, 2132] Port "31" IconDisplay "Port number" } Block { BlockType Inport Name "In30" Position [45, 2183, 75, 2197] Port "32" IconDisplay "Port number" } Block { BlockType Inport Name "In31" Position [45, 2248, 75, 2262] Port "33" IconDisplay "Port number" } Block { BlockType Inport Name "Start" Position [813, 35, 827, 65] Orientation "down" NamePlacement "alternate" Port "34" IconDisplay "Port number" } Block { BlockType SubSystem Name "And32" Ports [32, 1] Position [1044, 140, 1696, 190] Orientation "up" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And32" Location [2, 82, 1421, 854] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A1" Position [55, 58, 85, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A2" Position [55, 83, 85, 97] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A3" Position [55, 108, 85, 122] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A4" Position [55, 133, 85, 147] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A5" Position [55, 158, 85, 172] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A6" Position [55, 183, 85, 197] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A7" Position [55, 208, 85, 222] Port "7" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A8" Position [55, 233, 85, 247] Port "8" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A9" Position [55, 258, 85, 272] Port "9" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A10" Position [55, 283, 85, 297] Port "10" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A11" Position [55, 308, 85, 322] Port "11" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A12" Position [55, 333, 85, 347] Port "12" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A13" Position [55, 358, 85, 372] Port "13" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A14" Position [55, 383, 85, 397] Port "14" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A15" Position [55, 408, 85, 422] Port "15" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A16" Position [55, 433, 85, 447] Port "16" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A17" Position [60, 458, 90, 472] Port "17" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A18" Position [60, 483, 90, 497] Port "18" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A19" Position [60, 508, 90, 522] Port "19" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A20" Position [60, 533, 90, 547] Port "20" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A21" Position [60, 558, 90, 572] Port "21" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A22" Position [60, 583, 90, 597] Port "22" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A23" Position [60, 608, 90, 622] Port "23" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A24" Position [60, 633, 90, 647] Port "24" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A25" Position [60, 658, 90, 672] Port "25" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A26" Position [60, 683, 90, 697] Port "26" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A27" Position [60, 708, 90, 722] Port "27" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A28" Position [60, 733, 90, 747] Port "28" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A29" Position [60, 758, 90, 772] Port "29" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A30" Position [60, 783, 90, 797] Port "30" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A31" Position [60, 808, 90, 822] Port "31" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A32" Position [60, 833, 90, 847] Port "32" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [190, 438, 225, 472] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [32, 1] Position [120, 17, 165, 888] Inputs "32" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [245, 448, 275, 462] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A32" SrcPort 1 DstBlock "Logical\nOperator" DstPort 32 } Line { SrcBlock "A31" SrcPort 1 DstBlock "Logical\nOperator" DstPort 31 } Line { SrcBlock "A30" SrcPort 1 DstBlock "Logical\nOperator" DstPort 30 } Line { SrcBlock "A29" SrcPort 1 DstBlock "Logical\nOperator" DstPort 29 } Line { SrcBlock "A28" SrcPort 1 DstBlock "Logical\nOperator" DstPort 28 } Line { SrcBlock "A27" SrcPort 1 DstBlock "Logical\nOperator" DstPort 27 } Line { SrcBlock "A26" SrcPort 1 DstBlock "Logical\nOperator" DstPort 26 } Line { SrcBlock "A25" SrcPort 1 DstBlock "Logical\nOperator" DstPort 25 } Line { SrcBlock "A24" SrcPort 1 DstBlock "Logical\nOperator" DstPort 24 } Line { SrcBlock "A23" SrcPort 1 DstBlock "Logical\nOperator" DstPort 23 } Line { SrcBlock "A22" SrcPort 1 DstBlock "Logical\nOperator" DstPort 22 } Line { SrcBlock "A21" SrcPort 1 DstBlock "Logical\nOperator" DstPort 21 } Line { SrcBlock "A20" SrcPort 1 DstBlock "Logical\nOperator" DstPort 20 } Line { SrcBlock "A19" SrcPort 1 DstBlock "Logical\nOperator" DstPort 19 } Line { SrcBlock "A18" SrcPort 1 DstBlock "Logical\nOperator" DstPort 18 } Line { SrcBlock "A17" SrcPort 1 DstBlock "Logical\nOperator" DstPort 17 } Line { SrcBlock "A16" SrcPort 1 DstBlock "Logical\nOperator" DstPort 16 } Line { SrcBlock "A15" SrcPort 1 DstBlock "Logical\nOperator" DstPort 15 } Line { SrcBlock "A14" SrcPort 1 DstBlock "Logical\nOperator" DstPort 14 } Line { SrcBlock "A13" SrcPort 1 DstBlock "Logical\nOperator" DstPort 13 } Line { SrcBlock "A12" SrcPort 1 DstBlock "Logical\nOperator" DstPort 12 } Line { SrcBlock "A11" SrcPort 1 DstBlock "Logical\nOperator" DstPort 11 } Line { SrcBlock "A10" SrcPort 1 DstBlock "Logical\nOperator" DstPort 10 } Line { SrcBlock "A9" SrcPort 1 DstBlock "Logical\nOperator" DstPort 9 } Line { SrcBlock "A8" SrcPort 1 DstBlock "Logical\nOperator" DstPort 8 } Line { SrcBlock "A7" SrcPort 1 DstBlock "Logical\nOperator" DstPort 7 } Line { SrcBlock "A6" SrcPort 1 DstBlock "Logical\nOperator" DstPort 6 } Line { SrcBlock "A5" SrcPort 1 DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "A4" SrcPort 1 DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "A3" SrcPort 1 DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "A2" SrcPort 1 DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A1" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Decode32" Ports [6, 33] Position [210, 130, 880, 195] Orientation "down" ForegroundColor "yellow" BackgroundColor "cyan" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Decode32" Location [2, 82, 1421, 837] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "S4" Position [25, 28, 55, 42] IconDisplay "Port number" } Block { BlockType Inport Name "S3" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" } Block { BlockType Inport Name "S2" Position [25, 323, 55, 337] Port "3" IconDisplay "Port number" } Block { BlockType Inport Name "S1" Position [25, 458, 55, 472] Port "4" IconDisplay "Port number" } Block { BlockType Inport Name "S0" Position [25, 603, 55, 617] Port "5" IconDisplay "Port number" } Block { BlockType Inport Name "Start" Position [25, 763, 55, 777] Port "6" IconDisplay "Port number" } Block { BlockType SubSystem Name "And10" Ports [10, 1] Position [230, 709, 280, 876] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And10" Location [2, 78, 1438, 850] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 98, 55, 112] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 133, 55, 147] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 168, 55, 182] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "F" Position [25, 203, 55, 217] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "G" Position [25, 238, 55, 252] Port "7" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "H" Position [25, 273, 55, 287] Port "8" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "I" Position [25, 308, 55, 322] Port "9" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "J" Position [25, 343, 55, 357] Port "10" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 178, 230, 212] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [10, 1] Position [120, 14, 155, 371] Inputs "10" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [265, 188, 295, 202] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "F" SrcPort 1 DstBlock "Logical\nOperator" DstPort 6 } Line { SrcBlock "G" SrcPort 1 DstBlock "Logical\nOperator" DstPort 7 } Line { SrcBlock "H" SrcPort 1 DstBlock "Logical\nOperator" DstPort 8 } Line { SrcBlock "I" SrcPort 1 DstBlock "Logical\nOperator" DstPort 9 } Line { SrcBlock "J" SrcPort 1 DstBlock "Logical\nOperator" DstPort 10 } } } Block { BlockType SubSystem Name "And32" Ports [32, 1] Position [317, 1150, 4908, 1190] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And32" Location [2, 82, 1421, 854] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A1" Position [55, 58, 85, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A2" Position [55, 83, 85, 97] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A3" Position [55, 108, 85, 122] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A4" Position [55, 133, 85, 147] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A5" Position [55, 158, 85, 172] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A6" Position [55, 183, 85, 197] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A7" Position [55, 208, 85, 222] Port "7" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A8" Position [55, 233, 85, 247] Port "8" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A9" Position [55, 258, 85, 272] Port "9" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A10" Position [55, 283, 85, 297] Port "10" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A11" Position [55, 308, 85, 322] Port "11" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A12" Position [55, 333, 85, 347] Port "12" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A13" Position [55, 358, 85, 372] Port "13" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A14" Position [55, 383, 85, 397] Port "14" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A15" Position [55, 408, 85, 422] Port "15" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A16" Position [55, 433, 85, 447] Port "16" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A17" Position [60, 458, 90, 472] Port "17" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A18" Position [60, 483, 90, 497] Port "18" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A19" Position [60, 508, 90, 522] Port "19" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A20" Position [60, 533, 90, 547] Port "20" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A21" Position [60, 558, 90, 572] Port "21" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A22" Position [60, 583, 90, 597] Port "22" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A23" Position [60, 608, 90, 622] Port "23" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A24" Position [60, 633, 90, 647] Port "24" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A25" Position [60, 658, 90, 672] Port "25" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A26" Position [60, 683, 90, 697] Port "26" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A27" Position [60, 708, 90, 722] Port "27" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A28" Position [60, 733, 90, 747] Port "28" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A29" Position [60, 758, 90, 772] Port "29" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A30" Position [60, 783, 90, 797] Port "30" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A31" Position [60, 808, 90, 822] Port "31" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "A32" Position [60, 833, 90, 847] Port "32" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [190, 438, 225, 472] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [32, 1] Position [120, 17, 165, 888] Inputs "32" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [245, 448, 275, 462] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A1" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A2" SrcPort 1 DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A3" SrcPort 1 DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "A4" SrcPort 1 DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "A5" SrcPort 1 DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "A6" SrcPort 1 DstBlock "Logical\nOperator" DstPort 6 } Line { SrcBlock "A7" SrcPort 1 DstBlock "Logical\nOperator" DstPort 7 } Line { SrcBlock "A8" SrcPort 1 DstBlock "Logical\nOperator" DstPort 8 } Line { SrcBlock "A9" SrcPort 1 DstBlock "Logical\nOperator" DstPort 9 } Line { SrcBlock "A10" SrcPort 1 DstBlock "Logical\nOperator" DstPort 10 } Line { SrcBlock "A11" SrcPort 1 DstBlock "Logical\nOperator" DstPort 11 } Line { SrcBlock "A12" SrcPort 1 DstBlock "Logical\nOperator" DstPort 12 } Line { SrcBlock "A13" SrcPort 1 DstBlock "Logical\nOperator" DstPort 13 } Line { SrcBlock "A14" SrcPort 1 DstBlock "Logical\nOperator" DstPort 14 } Line { SrcBlock "A15" SrcPort 1 DstBlock "Logical\nOperator" DstPort 15 } Line { SrcBlock "A16" SrcPort 1 DstBlock "Logical\nOperator" DstPort 16 } Line { SrcBlock "A17" SrcPort 1 DstBlock "Logical\nOperator" DstPort 17 } Line { SrcBlock "A18" SrcPort 1 DstBlock "Logical\nOperator" DstPort 18 } Line { SrcBlock "A19" SrcPort 1 DstBlock "Logical\nOperator" DstPort 19 } Line { SrcBlock "A20" SrcPort 1 DstBlock "Logical\nOperator" DstPort 20 } Line { SrcBlock "A21" SrcPort 1 DstBlock "Logical\nOperator" DstPort 21 } Line { SrcBlock "A22" SrcPort 1 DstBlock "Logical\nOperator" DstPort 22 } Line { SrcBlock "A23" SrcPort 1 DstBlock "Logical\nOperator" DstPort 23 } Line { SrcBlock "A24" SrcPort 1 DstBlock "Logical\nOperator" DstPort 24 } Line { SrcBlock "A25" SrcPort 1 DstBlock "Logical\nOperator" DstPort 25 } Line { SrcBlock "A26" SrcPort 1 DstBlock "Logical\nOperator" DstPort 26 } Line { SrcBlock "A27" SrcPort 1 DstBlock "Logical\nOperator" DstPort 27 } Line { SrcBlock "A28" SrcPort 1 DstBlock "Logical\nOperator" DstPort 28 } Line { SrcBlock "A29" SrcPort 1 DstBlock "Logical\nOperator" DstPort 29 } Line { SrcBlock "A30" SrcPort 1 DstBlock "Logical\nOperator" DstPort 30 } Line { SrcBlock "A31" SrcPort 1 DstBlock "Logical\nOperator" DstPort 31 } Line { SrcBlock "A32" SrcPort 1 DstBlock "Logical\nOperator" DstPort 32 } } } Block { BlockType SubSystem Name "a_And0" Ports [6, 2] Position [303, 840, 402, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And0" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And1" Ports [6, 2] Position [443, 840, 542, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And1" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And10" Ports [6, 2] Position [1723, 840, 1822, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And10" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And11" Ports [6, 2] Position [1878, 840, 1977, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And11" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And12" Ports [6, 2] Position [2028, 835, 2127, 920] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And12" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And13" Ports [6, 2] Position [2173, 830, 2272, 915] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And13" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And14" Ports [6, 2] Position [2318, 830, 2417, 915] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And14" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And15" Ports [6, 2] Position [2468, 830, 2567, 915] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And15" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And16" Ports [6, 2] Position [2613, 830, 2712, 915] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And16" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And17" Ports [6, 2] Position [2763, 835, 2862, 920] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And17" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And18" Ports [6, 2] Position [2903, 835, 3002, 920] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And18" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And19" Ports [6, 2] Position [3048, 835, 3147, 920] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And19" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And2" Ports [6, 2] Position [588, 840, 687, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And2" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And20" Ports [6, 2] Position [3203, 840, 3302, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And20" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And21" Ports [6, 2] Position [3353, 840, 3452, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And21" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And22" Ports [6, 2] Position [3493, 840, 3592, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And22" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And23" Ports [6, 2] Position [3638, 840, 3737, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And23" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And24" Ports [6, 2] Position [3783, 840, 3882, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And24" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And25" Ports [6, 2] Position [3923, 840, 4022, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And25" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And26" Ports [6, 2] Position [4063, 840, 4162, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And26" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And27" Ports [6, 2] Position [4203, 840, 4302, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And27" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And28" Ports [6, 2] Position [4343, 840, 4442, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And28" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And29" Ports [6, 2] Position [4483, 840, 4582, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And29" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And3" Ports [6, 2] Position [733, 840, 832, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And3" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And30" Ports [6, 2] Position [4628, 835, 4727, 920] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And30" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And31" Ports [6, 2] Position [4773, 835, 4872, 920] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And31" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And4" Ports [6, 2] Position [878, 840, 977, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And4" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And5" Ports [6, 2] Position [1018, 840, 1117, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And5" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And6" Ports [6, 2] Position [1153, 840, 1252, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And6" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And7" Ports [6, 2] Position [1293, 840, 1392, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And7" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And8" Ports [6, 2] Position [1433, 840, 1532, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And8" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } } } Block { BlockType SubSystem Name "a_And9" Ports [6, 2] Position [1578, 840, 1677, 925] Orientation "down" NamePlacement "alternate" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And9" Location [239, 203, 881, 684] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [40, 33, 70, 47] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [40, 63, 70, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [40, 93, 70, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [40, 123, 70, 137] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [40, 153, 70, 167] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 218, 55, 232] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And5" Ports [5, 1] Position [130, 44, 180, 126] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And5" Location [546, 258, 923, 572] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "D" Position [25, 128, 55, 142] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "E" Position [25, 163, 55, 177] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [5, 1] Position [120, 28, 155, 132] Inputs "5" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -10] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 Points [0, -35] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "D" SrcPort 1 Points [35, 0; 0, -35] DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "E" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 5 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "E" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 5 } Line { SrcBlock "D" SrcPort 1 Points [30, 0; 0, -30] DstBlock "And5" DstPort 4 } Line { SrcBlock "C" SrcPort 1 Points [20, 0; 0, -15] DstBlock "And5" DstPort 3 } Line { SrcBlock "A" SrcPort 1 Points [40, 0] DstBlock "And5" DstPort 1 } Line { SrcBlock "B" SrcPort 1 DstBlock "And5" DstPort 2 } Line { SrcBlock "And5" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -70] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_Buf" Ports [2, 2] Position [120, 24, 205, 71] BackgroundColor "green" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Buf" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] ForegroundColor "red" BackgroundColor "cyan" SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Buf" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Buf" DstPort 1 } } } Block { BlockType SubSystem Name "a_Buf1" Ports [2, 2] Position [120, 174, 205, 221] BackgroundColor "green" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Buf1" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Buf" DstPort 1 } Line { SrcBlock "Buf" SrcPort 1 Points [10, 0] Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_Buf2" Ports [2, 2] Position [120, 319, 205, 366] BackgroundColor "green" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Buf2" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Buf" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Buf" DstPort 1 } } } Block { BlockType SubSystem Name "a_Buf3" Ports [2, 2] Position [120, 454, 205, 501] BackgroundColor "green" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Buf3" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Buf" DstPort 1 } Line { SrcBlock "Buf" SrcPort 1 Points [10, 0] Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_Buf4" Ports [2, 2] Position [120, 599, 205, 646] BackgroundColor "green" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Buf4" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 38, 55, 52] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType DataTypeConversion Name "Data Type Conversion" Position [80, 28, 155, 62] OutDataTypeMode "boolean" RndMeth "Floor" SaturateOnIntegerOverflow off } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [185, 28, 220, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Data Type Conversion" DstPort 1 } Line { SrcBlock "Data Type Conversion" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Buf" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Buf" DstPort 1 } } } Block { BlockType SubSystem Name "a_Not" Ports [2, 2] Position [120, 89, 205, 136] BackgroundColor "red" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Not" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Not" DstPort 1 } Line { SrcBlock "Not" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_Not1" Ports [2, 2] Position [120, 239, 205, 286] BackgroundColor "red" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Not1" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Not" DstPort 1 } } } Block { BlockType SubSystem Name "a_Not2" Ports [2, 2] Position [120, 384, 205, 431] BackgroundColor "red" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Not2" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Not" DstPort 1 } Line { SrcBlock "Not" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_Not3" Ports [2, 2] Position [120, 519, 205, 566] BackgroundColor "red" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Not3" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Not" DstPort 1 } } } Block { BlockType SubSystem Name "a_Not4" Ports [2, 2] Position [120, 664, 205, 711] BackgroundColor "red" MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Not4" Location [445, 342, 995, 558] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not" Ports [1, 1] Position [130, 69, 180, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins "[0.500000, 0.500000, 0.500000, 0.5000" "00]" TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "Not" DstPort 1 } Line { SrcBlock "Not" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType Outport Name "Out0" Position [323, 1080, 337, 1110] Orientation "down" NamePlacement "alternate" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out1" Position [463, 1080, 477, 1110] Orientation "down" NamePlacement "alternate" Port "2" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out2" Position [608, 1085, 622, 1115] Orientation "down" NamePlacement "alternate" Port "3" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out3" Position [753, 1085, 767, 1115] Orientation "down" NamePlacement "alternate" Port "4" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out4" Position [898, 1085, 912, 1115] Orientation "down" NamePlacement "alternate" Port "5" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out5" Position [1038, 1085, 1052, 1115] Orientation "down" NamePlacement "alternate" Port "6" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out6" Position [1173, 1085, 1187, 1115] Orientation "down" NamePlacement "alternate" Port "7" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out7" Position [1313, 1085, 1327, 1115] Orientation "down" NamePlacement "alternate" Port "8" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out8" Position [1453, 1085, 1467, 1115] Orientation "down" NamePlacement "alternate" Port "9" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out9" Position [1598, 1080, 1612, 1110] Orientation "down" NamePlacement "alternate" Port "10" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out10" Position [1743, 1080, 1757, 1110] Orientation "down" NamePlacement "alternate" Port "11" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out11" Position [1898, 1080, 1912, 1110] Orientation "down" NamePlacement "alternate" Port "12" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out12" Position [2048, 1080, 2062, 1110] Orientation "down" NamePlacement "alternate" Port "13" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out13" Position [2193, 1080, 2207, 1110] Orientation "down" NamePlacement "alternate" Port "14" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out14" Position [2338, 1080, 2352, 1110] Orientation "down" NamePlacement "alternate" Port "15" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out15" Position [2488, 1080, 2502, 1110] Orientation "down" NamePlacement "alternate" Port "16" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out16" Position [2633, 1080, 2647, 1110] Orientation "down" NamePlacement "alternate" Port "17" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out17" Position [2783, 1080, 2797, 1110] Orientation "down" NamePlacement "alternate" Port "18" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out18" Position [2923, 1080, 2937, 1110] Orientation "down" NamePlacement "alternate" Port "19" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out19" Position [3068, 1080, 3082, 1110] Orientation "down" NamePlacement "alternate" Port "20" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out20" Position [3223, 1080, 3237, 1110] Orientation "down" NamePlacement "alternate" Port "21" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out21" Position [3373, 1080, 3387, 1110] Orientation "down" NamePlacement "alternate" Port "22" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out22" Position [3513, 1080, 3527, 1110] Orientation "down" NamePlacement "alternate" Port "23" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out23" Position [3658, 1080, 3672, 1110] Orientation "down" NamePlacement "alternate" Port "24" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out24" Position [3803, 1080, 3817, 1110] Orientation "down" NamePlacement "alternate" Port "25" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out25" Position [3943, 1080, 3957, 1110] Orientation "down" NamePlacement "alternate" Port "26" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out26" Position [4083, 1080, 4097, 1110] Orientation "down" NamePlacement "alternate" Port "27" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out27" Position [4223, 1080, 4237, 1110] Orientation "down" NamePlacement "alternate" Port "28" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out28" Position [4363, 1080, 4377, 1110] Orientation "down" NamePlacement "alternate" Port "29" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out29" Position [4503, 1080, 4517, 1110] Orientation "down" NamePlacement "alternate" Port "30" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out30" Position [4648, 1080, 4662, 1110] Orientation "down" NamePlacement "alternate" Port "31" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Out31" Position [4793, 1075, 4807, 1105] Orientation "down" NamePlacement "alternate" Port "32" IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Finish1" Position [2608, 1270, 2622, 1300] Orientation "down" NamePlacement "alternate" Port "33" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "And32" SrcPort 1 DstBlock "Finish1" DstPort 1 } Line { SrcBlock "a_And31" SrcPort 2 Points [0, 110; 10, 0] DstBlock "And32" DstPort 32 } Line { SrcBlock "a_And30" SrcPort 2 Points [0, 110; 10, 0] DstBlock "And32" DstPort 31 } Line { SrcBlock "a_And29" SrcPort 2 Points [0, 110; 10, 0] DstBlock "And32" DstPort 30 } Line { SrcBlock "a_And28" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 29 } Line { SrcBlock "a_And27" SrcPort 2 DstBlock "And32" DstPort 28 } Line { SrcBlock "a_And26" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 27 } Line { SrcBlock "a_And25" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 26 } Line { SrcBlock "a_And24" SrcPort 2 Points [0, 110; -15, 0] DstBlock "And32" DstPort 25 } Line { SrcBlock "a_And23" SrcPort 2 Points [0, 110; -15, 0] DstBlock "And32" DstPort 24 } Line { SrcBlock "a_And22" SrcPort 2 Points [0, 110; -15, 0] DstBlock "And32" DstPort 23 } Line { SrcBlock "a_And21" SrcPort 2 Points [0, 110; -20, 0] DstBlock "And32" DstPort 22 } Line { SrcBlock "a_And20" SrcPort 2 Points [0, 110; -15, 0] DstBlock "And32" DstPort 21 } Line { SrcBlock "a_And19" SrcPort 2 Points [0, 210] DstBlock "And32" DstPort 20 } Line { SrcBlock "a_And18" SrcPort 2 Points [0, 210] DstBlock "And32" DstPort 19 } Line { SrcBlock "a_And17" SrcPort 2 Points [0, 210] DstBlock "And32" DstPort 18 } Line { SrcBlock "a_And16" SrcPort 2 Points [0, 215] DstBlock "And32" DstPort 17 } Line { SrcBlock "a_And15" SrcPort 2 Points [0, 215] DstBlock "And32" DstPort 16 } Line { SrcBlock "a_And14" SrcPort 2 DstBlock "And32" DstPort 15 } Line { SrcBlock "a_And13" SrcPort 2 DstBlock "And32" DstPort 14 } Line { SrcBlock "a_And12" SrcPort 2 DstBlock "And32" DstPort 13 } Line { SrcBlock "a_And11" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 12 } Line { SrcBlock "a_And10" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 11 } Line { SrcBlock "a_And9" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 10 } Line { SrcBlock "a_And8" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 9 } Line { SrcBlock "a_And7" SrcPort 2 Points [0, 110; 10, 0] DstBlock "And32" DstPort 8 } Line { SrcBlock "a_And6" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 7 } Line { SrcBlock "a_And5" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 6 } Line { SrcBlock "a_And4" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 5 } Line { SrcBlock "a_And3" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 4 } Line { SrcBlock "a_And2" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 3 } Line { SrcBlock "a_And1" SrcPort 2 Points [0, 205] DstBlock "And32" DstPort 2 } Line { SrcBlock "a_And0" SrcPort 2 Points [0, 110; -15, 0] DstBlock "And32" DstPort 1 } Line { SrcBlock "a_And31" SrcPort 1 DstBlock "Out31" DstPort 1 } Line { SrcBlock "a_And30" SrcPort 1 DstBlock "Out30" DstPort 1 } Line { SrcBlock "a_And29" SrcPort 1 DstBlock "Out29" DstPort 1 } Line { SrcBlock "a_And28" SrcPort 1 DstBlock "Out28" DstPort 1 } Line { SrcBlock "a_And27" SrcPort 1 DstBlock "Out27" DstPort 1 } Line { SrcBlock "a_And26" SrcPort 1 DstBlock "Out26" DstPort 1 } Line { SrcBlock "a_And25" SrcPort 1 DstBlock "Out25" DstPort 1 } Line { SrcBlock "a_And24" SrcPort 1 DstBlock "Out24" DstPort 1 } Line { SrcBlock "a_And23" SrcPort 1 DstBlock "Out23" DstPort 1 } Line { SrcBlock "a_And22" SrcPort 1 DstBlock "Out22" DstPort 1 } Line { SrcBlock "a_And21" SrcPort 1 DstBlock "Out21" DstPort 1 } Line { SrcBlock "a_And20" SrcPort 1 DstBlock "Out20" DstPort 1 } Line { SrcBlock "a_And19" SrcPort 1 DstBlock "Out19" DstPort 1 } Line { SrcBlock "a_And18" SrcPort 1 DstBlock "Out18" DstPort 1 } Line { SrcBlock "a_And17" SrcPort 1 DstBlock "Out17" DstPort 1 } Line { SrcBlock "a_And16" SrcPort 1 DstBlock "Out16" DstPort 1 } Line { SrcBlock "a_And15" SrcPort 1 DstBlock "Out15" DstPort 1 } Line { SrcBlock "a_And14" SrcPort 1 DstBlock "Out14" DstPort 1 } Line { SrcBlock "a_And13" SrcPort 1 DstBlock "Out13" DstPort 1 } Line { SrcBlock "a_And12" SrcPort 1 DstBlock "Out12" DstPort 1 } Line { SrcBlock "a_And11" SrcPort 1 DstBlock "Out11" DstPort 1 } Line { SrcBlock "a_And10" SrcPort 1 DstBlock "Out10" DstPort 1 } Line { SrcBlock "a_And9" SrcPort 1 DstBlock "Out9" DstPort 1 } Line { SrcBlock "a_And8" SrcPort 1 DstBlock "Out8" DstPort 1 } Line { SrcBlock "a_And7" SrcPort 1 DstBlock "Out7" DstPort 1 } Line { SrcBlock "a_And6" SrcPort 1 DstBlock "Out6" DstPort 1 } Line { SrcBlock "a_And5" SrcPort 1 DstBlock "Out5" DstPort 1 } Line { SrcBlock "a_And4" SrcPort 1 DstBlock "Out4" DstPort 1 } Line { SrcBlock "a_And3" SrcPort 1 DstBlock "Out3" DstPort 1 } Line { SrcBlock "a_And2" SrcPort 1 DstBlock "Out2" DstPort 1 } Line { SrcBlock "a_And1" SrcPort 1 DstBlock "Out1" DstPort 1 } Line { SrcBlock "a_And0" SrcPort 1 DstBlock "Out0" DstPort 1 } Line { SrcBlock "And10" SrcPort 1 Points [105, 0] Branch { DstBlock "a_And0" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And1" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And2" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And3" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And4" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And5" DstPort 6 } Branch { Points [135, 0] Branch { DstBlock "a_And6" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And7" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And8" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And9" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And10" DstPort 6 } Branch { Points [155, 0] Branch { DstBlock "a_And11" DstPort 6 } Branch { Points [150, 0] Branch { DstBlock "a_And12" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And13" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And14" DstPort 6 } Branch { Points [150, 0] Branch { DstBlock "a_And15" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And16" DstPort 6 } Branch { Points [150, 0] Branch { DstBlock "a_And17" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And18" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And19" DstPort 6 } Branch { Points [155, 0] Branch { DstBlock "a_And20" DstPort 6 } Branch { Points [150, 0] Branch { DstBlock "a_And21" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And22" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And23" DstPort 6 } Branch { Points [145, 0] Branch { DstBlock "a_And24" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And25" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And26" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And27" DstPort 6 } Branch { Points [140, 0] Branch { DstBlock "a_And28" DstPort 6 } Branch { Points [140, 0] Branch { Points [145, 0] Branch { DstBlock "a_And30" DstPort 6 } Branch { Points [145, 0] DstBlock "a_And31" DstPort 6 } } Branch { DstBlock "a_And29" DstPort 6 } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } Line { SrcBlock "a_Not4" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 10 } Line { SrcBlock "a_Buf4" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 9 } Line { SrcBlock "a_Not3" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 8 } Line { SrcBlock "a_Buf3" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 7 } Line { SrcBlock "a_Not2" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 6 } Line { SrcBlock "a_Buf2" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 5 } Line { SrcBlock "a_Not1" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 4 } Line { SrcBlock "a_Buf1" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 3 } Line { SrcBlock "a_Not" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 2 } Line { SrcBlock "a_Buf" SrcPort 2 Points [5, 0] DstBlock "And10" DstPort 1 } Line { SrcBlock "a_Buf4" SrcPort 1 Points [305, 0] Branch { DstBlock "a_And1" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And3" DstPort 5 } Branch { Points [285, 0] Branch { DstBlock "a_And5" DstPort 5 } Branch { Points [275, 0] Branch { DstBlock "a_And7" DstPort 5 } Branch { Points [285, 0] Branch { DstBlock "a_And9" DstPort 5 } Branch { Points [300, 0] Branch { DstBlock "a_And11" DstPort 5 } Branch { Points [295, 0] Branch { DstBlock "a_And13" DstPort 5 } Branch { Points [295, 0] Branch { DstBlock "a_And15" DstPort 5 } Branch { Points [295, 0] Branch { DstBlock "a_And17" DstPort 5 } Branch { Points [285, 0] Branch { DstBlock "a_And19" DstPort 5 } Branch { Points [305, 0] Branch { DstBlock "a_And21" DstPort 5 } Branch { Points [285, 0] Branch { DstBlock "a_And23" DstPort 5 } Branch { Points [285, 0] Branch { DstBlock "a_And25" DstPort 5 } Branch { Points [280, 0] Branch { DstBlock "a_And27" DstPort 5 } Branch { Points [280, 0] Branch { DstBlock "a_And29" DstPort 5 } Branch { Points [290, 0] DstBlock "a_And31" DstPort 5 } } } } } } } } } } } } } } } } Line { SrcBlock "a_Not3" SrcPort 1 Points [150, 0] Branch { DstBlock "a_And0" DstPort 4 } Branch { Points [140, 0] Branch { DstBlock "a_And1" DstPort 4 } Branch { Points [435, 0] Branch { DstBlock "a_And4" DstPort 4 } Branch { Points [140, 0] Branch { DstBlock "a_And5" DstPort 4 } Branch { Points [415, 0] Branch { DstBlock "a_And8" DstPort 4 } Branch { Points [145, 0] Branch { DstBlock "a_And9" DstPort 4 } Branch { Points [450, 0] Branch { DstBlock "a_And12" DstPort 4 } Branch { Points [145, 0] Branch { DstBlock "a_And13" DstPort 4 } Branch { Points [440, 0] Branch { DstBlock "a_And16" DstPort 4 } Branch { Points [150, 0] Branch { DstBlock "a_And17" DstPort 4 } Branch { Points [440, 0] Branch { DstBlock "a_And20" DstPort 4 } Branch { Points [150, 0] Branch { DstBlock "a_And21" DstPort 4 } Branch { Points [430, 0] Branch { DstBlock "a_And24" DstPort 4 } Branch { Points [140, 0] Branch { DstBlock "a_And25" DstPort 4 } Branch { Points [420, 0] Branch { DstBlock "a_And28" DstPort 4 } Branch { Points [140, 0] DstBlock "a_And29" DstPort 4 } } } } } } } } } } } } } } } } Line { SrcBlock "a_Buf3" SrcPort 1 Points [435, 0] Branch { DstBlock "a_And2" DstPort 4 } Branch { Points [145, 0] Branch { DstBlock "a_And3" DstPort 4 } Branch { Points [420, 0] Branch { DstBlock "a_And6" DstPort 4 } Branch { Points [140, 0] Branch { DstBlock "a_And7" DstPort 4 } Branch { Points [430, 0] Branch { DstBlock "a_And10" DstPort 4 } Branch { Points [155, 0] Branch { DstBlock "a_And11" DstPort 4 } Branch { Points [440, 0] Branch { DstBlock "a_And14" DstPort 4 } Branch { Points [150, 0] Branch { DstBlock "a_And15" DstPort 4 } Branch { Points [435, 0] Branch { DstBlock "a_And18" DstPort 4 } Branch { Points [145, 0] Branch { DstBlock "a_And19" DstPort 4 } Branch { Points [445, 0] Branch { DstBlock "a_And22" DstPort 4 } Branch { Points [145, 0] Branch { DstBlock "a_And23" DstPort 4 } Branch { Points [425, 0] Branch { DstBlock "a_And26" DstPort 4 } Branch { Points [140, 0] Branch { DstBlock "a_And27" DstPort 4 } Branch { Points [425, 0] Branch { DstBlock "a_And30" DstPort 4 } Branch { Points [145, 0] DstBlock "a_And31" DstPort 4 } } } } } } } } } } } } } } } } Line { SrcBlock "a_Not2" SrcPort 1 Points [135, 0] Branch { DstBlock "a_And0" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And1" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And2" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And3" DstPort 3 } Branch { Points [700, 0] Branch { DstBlock "a_And8" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And9" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And10" DstPort 3 } Branch { Points [155, 0] Branch { DstBlock "a_And11" DstPort 3 } Branch { Points [735, 0] Branch { DstBlock "a_And16" DstPort 3 } Branch { Points [150, 0] Branch { DstBlock "a_And17" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And18" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And19" DstPort 3 } Branch { Points [735, 0] Branch { DstBlock "a_And24" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And25" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And26" DstPort 3 } Branch { Points [140, 0] DstBlock "a_And27" DstPort 3 } } } } } } } } } } } } } } } } Line { SrcBlock "a_Buf2" SrcPort 1 Points [710, 0] Branch { DstBlock "a_And4" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And5" DstPort 3 } Branch { Points [135, 0] Branch { DstBlock "a_And6" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And7" DstPort 3 } Branch { Points [735, 0] Branch { DstBlock "a_And12" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And13" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And14" DstPort 3 } Branch { Points [150, 0] Branch { DstBlock "a_And15" DstPort 3 } Branch { Points [735, 0] Branch { DstBlock "a_And20" DstPort 3 } Branch { Points [150, 0] Branch { DstBlock "a_And21" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And22" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And23" DstPort 3 } Branch { Points [705, 0] Branch { DstBlock "a_And28" DstPort 3 } Branch { Points [140, 0] Branch { DstBlock "a_And29" DstPort 3 } Branch { Points [145, 0] Branch { DstBlock "a_And30" DstPort 3 } Branch { Points [145, 0] DstBlock "a_And31" DstPort 3 } } } } } } } } } } } } } } } } Line { SrcBlock "a_Not1" SrcPort 1 Points [120, 0] Branch { DstBlock "a_And0" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And1" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And2" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And3" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And4" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And5" DstPort 2 } Branch { Points [135, 0] Branch { DstBlock "a_And6" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And7" DstPort 2 } Branch { Points [1320, 0] Branch { DstBlock "a_And16" DstPort 2 } Branch { Points [150, 0] Branch { DstBlock "a_And17" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And18" DstPort 2 } Branch { Points [145, 0] Branch { Points [155, 0] Branch { DstBlock "a_And20" DstPort 2 } Branch { Points [150, 0] Branch { DstBlock "a_And21" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And22" DstPort 2 } Branch { Points [145, 0] DstBlock "a_And23" DstPort 2 } } } } Branch { DstBlock "a_And19" DstPort 2 } } } } } } } } } } } } } Line { SrcBlock "a_Buf1" SrcPort 1 Points [1250, 0] Branch { DstBlock "a_And8" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And9" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And10" DstPort 2 } Branch { Points [155, 0] Branch { DstBlock "a_And11" DstPort 2 } Branch { Points [150, 0] Branch { DstBlock "a_And12" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And13" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And14" DstPort 2 } Branch { Points [150, 0] Branch { DstBlock "a_And15" DstPort 2 } Branch { Points [1315, 0] Branch { DstBlock "a_And24" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And25" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And26" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And27" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And28" DstPort 2 } Branch { Points [140, 0] Branch { DstBlock "a_And29" DstPort 2 } Branch { Points [145, 0] Branch { DstBlock "a_And30" DstPort 2 } Branch { Points [145, 0] DstBlock "a_And31" DstPort 2 } } } } } } } } } } } } } } } } Line { SrcBlock "a_Not" SrcPort 1 Points [105, 0] Branch { DstBlock "a_And0" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And1" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And2" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And3" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And4" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And5" DstPort 1 } Branch { Points [135, 0] Branch { DstBlock "a_And6" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And7" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And8" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And9" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And10" DstPort 1 } Branch { Points [155, 0] Branch { DstBlock "a_And11" DstPort 1 } Branch { Points [150, 0] Branch { DstBlock "a_And12" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And13" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And14" DstPort 1 } Branch { Points [150, 0] DstBlock "a_And15" DstPort 1 } } } } } } } } } } } } } } } } Line { Labels [0, 0] SrcBlock "a_Buf" SrcPort 1 Points [2415, 0] Branch { DstBlock "a_And16" DstPort 1 } Branch { Points [150, 0] Branch { DstBlock "a_And17" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And18" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And19" DstPort 1 } Branch { Points [155, 0] Branch { DstBlock "a_And20" DstPort 1 } Branch { Points [150, 0] Branch { DstBlock "a_And21" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And22" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And23" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And24" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And25" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And26" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And27" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And28" DstPort 1 } Branch { Points [140, 0] Branch { DstBlock "a_And29" DstPort 1 } Branch { Points [145, 0] Branch { DstBlock "a_And30" DstPort 1 } Branch { Points [145, 0] DstBlock "a_And31" DstPort 1 } } } } } } } } } } } } } } } } Line { SrcBlock "Start" SrcPort 1 Points [30, 0; 0, -70] Branch { DstBlock "a_Not4" DstPort 2 } Branch { Points [0, -65] Branch { DstBlock "a_Buf4" DstPort 2 } Branch { Points [0, -80] Branch { DstBlock "a_Not3" DstPort 2 } Branch { Points [0, -65] Branch { DstBlock "a_Buf3" DstPort 2 } Branch { Points [0, -65] Branch { Points [15, 0] DstBlock "a_Not2" DstPort 2 } Branch { Points [0, -70] Branch { DstBlock "a_Buf2" DstPort 2 } Branch { Points [0, -80] Branch { Points [0, -65] Branch { DstBlock "a_Buf1" DstPort 2 } Branch { Points [0, -85] Branch { DstBlock "a_Not" DstPort 2 } Branch { Points [0, -65] DstBlock "a_Buf" DstPort 2 } } } Branch { DstBlock "a_Not1" DstPort 2 } } } } } } } } Line { SrcBlock "a_Not4" SrcPort 1 Points [165, 0] Branch { DstBlock "a_And0" DstPort 5 } Branch { Points [285, 0] Branch { DstBlock "a_And2" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And4" DstPort 5 } Branch { Points [275, 0] Branch { DstBlock "a_And6" DstPort 5 } Branch { Points [280, 0] Branch { DstBlock "a_And8" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And10" DstPort 5 } Branch { Points [305, 0] Branch { DstBlock "a_And12" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And14" DstPort 5 } Branch { Points [295, 0] Branch { DstBlock "a_And16" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And18" DstPort 5 } Branch { Points [300, 0] Branch { DstBlock "a_And20" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And22" DstPort 5 } Branch { Points [290, 0] Branch { DstBlock "a_And24" DstPort 5 } Branch { Points [280, 0] Branch { DstBlock "a_And26" DstPort 5 } Branch { Points [280, 0] Branch { DstBlock "a_And28" DstPort 5 } Branch { Points [285, 0] DstBlock "a_And30" DstPort 5 } } } } } } } } } } } } } } } } Line { SrcBlock "S0" SrcPort 1 Points [10, 0] Branch { DstBlock "a_Buf4" DstPort 1 } Branch { Points [0, 65] DstBlock "a_Not4" DstPort 1 } } Line { SrcBlock "S1" SrcPort 1 Points [10, 0] Branch { Points [0, 65] DstBlock "a_Not3" DstPort 1 } Branch { DstBlock "a_Buf3" DstPort 1 } } Line { SrcBlock "S2" SrcPort 1 Points [10, 0] Branch { Points [0, 65] DstBlock "a_Not2" DstPort 1 } Branch { DstBlock "a_Buf2" DstPort 1 } } Line { SrcBlock "S3" SrcPort 1 Points [10, 0] Branch { Points [0, 65] DstBlock "a_Not1" DstPort 1 } Branch { DstBlock "a_Buf1" DstPort 1 } } Line { SrcBlock "S4" SrcPort 1 Points [5, 0] Branch { Points [0, 65] DstBlock "a_Not" DstPort 1 } Branch { DstBlock "a_Buf" DstPort 1 } } } } Block { BlockType Demux Name "Demux" Ports [1, 5] Position [210, 85, 770, 95] Orientation "down" BackgroundColor "black" NamePlacement "alternate" ShowName off Outputs "5" DisplayOption "bar" } Block { BlockType SubSystem Name "a_And0" Ports [3, 2] Position [905, 232, 990, 278] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And0" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And1" Ports [3, 2] Position [905, 297, 990, 343] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And1" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And10" Ports [3, 2] Position [905, 872, 990, 918] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And10" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And11" Ports [3, 2] Position [905, 937, 990, 983] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And11" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And12" Ports [3, 2] Position [905, 1002, 990, 1048] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And12" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And13" Ports [3, 2] Position [905, 1067, 990, 1113] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And13" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And14" Ports [3, 2] Position [905, 1137, 990, 1183] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And14" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And15" Ports [3, 2] Position [905, 1202, 990, 1248] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And15" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And16" Ports [3, 2] Position [905, 1267, 990, 1313] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And16" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And17" Ports [3, 2] Position [905, 1332, 990, 1378] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And17" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And18" Ports [3, 2] Position [905, 1397, 990, 1443] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And18" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And19" Ports [3, 2] Position [905, 1462, 990, 1508] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And19" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And2" Ports [3, 2] Position [905, 357, 990, 403] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And2" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And20" Ports [3, 2] Position [905, 1527, 990, 1573] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And20" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And21" Ports [3, 2] Position [905, 1592, 990, 1638] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And21" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And22" Ports [3, 2] Position [905, 1657, 990, 1703] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And22" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And23" Ports [3, 2] Position [905, 1722, 990, 1768] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And23" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And24" Ports [3, 2] Position [905, 1787, 990, 1833] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And24" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And25" Ports [3, 2] Position [905, 1857, 990, 1903] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And25" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And26" Ports [3, 2] Position [905, 1922, 990, 1968] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And26" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And27" Ports [3, 2] Position [905, 1987, 990, 2033] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And27" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And28" Ports [3, 2] Position [905, 2052, 990, 2098] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And28" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And29" Ports [3, 2] Position [905, 2117, 990, 2163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And29" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And3" Ports [3, 2] Position [905, 422, 990, 468] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And3" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And30" Ports [3, 2] Position [905, 2182, 990, 2228] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And30" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And31" Ports [3, 2] Position [905, 2247, 990, 2293] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And31" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And4" Ports [3, 2] Position [905, 482, 990, 528] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And4" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And5" Ports [3, 2] Position [905, 547, 990, 593] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And5" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And6" Ports [3, 2] Position [905, 612, 990, 658] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And6" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And7" Ports [3, 2] Position [905, 677, 990, 723] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And7" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_And8" Ports [3, 2] Position [905, 742, 990, 788] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And8" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, -50] DstBlock "Out" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { Points [0, -55] DstBlock "And2" DstPort 2 } Branch { DstBlock "And3" DstPort 2 } } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } } } Block { BlockType SubSystem Name "a_And9" Ports [3, 2] Position [905, 807, 990, 853] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_And9" Location [2057, 260, 2607, 476] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 58, 55, 72] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 93, 55, 107] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [25, 178, 55, 192] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And1" Ports [2, 1] Position [130, 67, 180, 98] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [250, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "And1" SrcPort 1 Points [10, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } Line { SrcBlock "B" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 2 } Line { SrcBlock "A" SrcPort 1 Points [55, 0] DstBlock "And1" DstPort 1 } } } Block { BlockType SubSystem Name "a_Or32" Ports [33, 2] Position [1740, 216, 1815, 2334] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "a_Or32" Location [395, 122, 999, 806] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "C1" Position [30, 228, 60, 242] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C2" Position [30, 248, 60, 262] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C3" Position [30, 268, 60, 282] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C4" Position [30, 288, 60, 302] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C5" Position [30, 308, 60, 322] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C6" Position [30, 328, 60, 342] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C7" Position [30, 348, 60, 362] Port "7" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C8" Position [30, 368, 60, 382] Port "8" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C9" Position [30, 388, 60, 402] Port "9" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C10" Position [30, 408, 60, 422] Port "10" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C11" Position [30, 428, 60, 442] Port "11" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C12" Position [30, 448, 60, 462] Port "12" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C13" Position [30, 468, 60, 482] Port "13" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C14" Position [30, 488, 60, 502] Port "14" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C15" Position [30, 508, 60, 522] Port "15" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C16" Position [30, 528, 60, 542] Port "16" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C17" Position [30, 548, 60, 562] Port "17" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C18" Position [30, 568, 60, 582] Port "18" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C19" Position [30, 588, 60, 602] Port "19" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C20" Position [30, 608, 60, 622] Port "20" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C21" Position [30, 628, 60, 642] Port "21" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C22" Position [30, 648, 60, 662] Port "22" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C23" Position [30, 668, 60, 682] Port "23" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C24" Position [30, 688, 60, 702] Port "24" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C25" Position [30, 708, 60, 722] Port "25" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C26" Position [30, 728, 60, 742] Port "26" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C27" Position [30, 748, 60, 762] Port "27" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C28" Position [30, 768, 60, 782] Port "28" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C29" Position [30, 788, 60, 802] Port "29" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C30" Position [30, 808, 60, 822] Port "30" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C31" Position [30, 828, 60, 842] Port "31" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C32" Position [30, 848, 60, 862] Port "32" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "Start" Position [30, 178, 60, 192] Port "33" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType SubSystem Name "And2" Ports [2, 1] Position [335, 77, 385, 108] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And2" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "And3" Ports [2, 1] Position [335, 132, 385, 163] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "And3" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Buf1" Ports [1, 1] Position [240, 69, 290, 101] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Buf1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "A" SrcPort 1 Points [45, 0; 0, 10] DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Not1" Ports [1, 1] Position [240, 124, 290, 156] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Not1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [1, 1] Position [120, 29, 150, 61] Operator "NOT" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } Line { SrcBlock "A" SrcPort 1 Points [45, 0] DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } } } Block { BlockType SubSystem Name "Or1" Ports [2, 1] Position [415, 107, 465, 138] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or1" Location [550, 399, 890, 501] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "A" Position [25, 28, 55, 42] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "B" Position [25, 63, 55, 77] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [195, 28, 230, 62] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [2, 1] Position [120, 27, 150, 58] Operator "OR" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [285, 38, 315, 52] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "B" SrcPort 1 Points [25, 0; 0, -20] DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "A" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType SubSystem Name "Or2" Ports [32, 1] Position [90, 220, 140, 870] MinAlgLoopOccurrences off RTWSystemCode "Auto" FunctionWithSeparateData off MaskHideContents off System { Name "Or2" Location [2, 82, 1438, 854] Open off ModelBrowserVisibility off ModelBrowserWidth 200 ScreenColor "white" PaperOrientation "landscape" PaperPositionMode "auto" PaperType "usletter" PaperUnits "inches" TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000] TiledPageScale 1 ShowPageBoundaries off ZoomFactor "100" Block { BlockType Inport Name "C1" Position [25, 53, 55, 67] IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C2" Position [25, 73, 55, 87] Port "2" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C3" Position [25, 93, 55, 107] Port "3" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C4" Position [25, 113, 55, 127] Port "4" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C5" Position [25, 133, 55, 147] Port "5" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C6" Position [25, 153, 55, 167] Port "6" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C7" Position [25, 173, 55, 187] Port "7" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C8" Position [25, 193, 55, 207] Port "8" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C9" Position [25, 213, 55, 227] Port "9" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C10" Position [25, 233, 55, 247] Port "10" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C11" Position [25, 253, 55, 267] Port "11" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C12" Position [25, 273, 55, 287] Port "12" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C13" Position [25, 293, 55, 307] Port "13" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C14" Position [25, 313, 55, 327] Port "14" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C15" Position [25, 333, 55, 347] Port "15" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C16" Position [25, 353, 55, 367] Port "16" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C17" Position [25, 373, 55, 387] Port "17" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C18" Position [25, 393, 55, 407] Port "18" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C19" Position [25, 413, 55, 427] Port "19" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C20" Position [25, 433, 55, 447] Port "20" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C21" Position [25, 453, 55, 467] Port "21" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C22" Position [25, 473, 55, 487] Port "22" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C23" Position [25, 493, 55, 507] Port "23" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C24" Position [25, 513, 55, 527] Port "24" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C25" Position [25, 533, 55, 547] Port "25" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C26" Position [25, 553, 55, 567] Port "26" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C27" Position [25, 573, 55, 587] Port "27" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C28" Position [25, 593, 55, 607] Port "28" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C29" Position [25, 613, 55, 627] Port "29" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C30" Position [25, 633, 55, 647] Port "30" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C31" Position [25, 653, 55, 667] Port "31" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Inport Name "C32" Position [25, 673, 55, 687] Port "32" IconDisplay "Port number" OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Reference Name "Integer Delay" Ports [1, 1] Position [180, 353, 215, 387] SourceBlock "simulink/Discrete/Integer Delay" SourceType "Integer Delay" vinit "0.0" samptime "-1" NumDelays "delay" } Block { BlockType Logic Name "Logical\nOperator" Ports [32, 1] Position [120, 17, 155, 723] Operator "OR" Inputs "32" AllPortsSameDT off OutDataTypeMode "Boolean" } Block { BlockType Outport Name "Out" Position [245, 363, 275, 377] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "C32" SrcPort 1 DstBlock "Logical\nOperator" DstPort 32 } Line { SrcBlock "C31" SrcPort 1 DstBlock "Logical\nOperator" DstPort 31 } Line { SrcBlock "C30" SrcPort 1 DstBlock "Logical\nOperator" DstPort 30 } Line { SrcBlock "C29" SrcPort 1 DstBlock "Logical\nOperator" DstPort 29 } Line { SrcBlock "C28" SrcPort 1 DstBlock "Logical\nOperator" DstPort 28 } Line { SrcBlock "C27" SrcPort 1 DstBlock "Logical\nOperator" DstPort 27 } Line { SrcBlock "C26" SrcPort 1 DstBlock "Logical\nOperator" DstPort 26 } Line { SrcBlock "C25" SrcPort 1 DstBlock "Logical\nOperator" DstPort 25 } Line { SrcBlock "C24" SrcPort 1 DstBlock "Logical\nOperator" DstPort 24 } Line { SrcBlock "C23" SrcPort 1 DstBlock "Logical\nOperator" DstPort 23 } Line { SrcBlock "C22" SrcPort 1 DstBlock "Logical\nOperator" DstPort 22 } Line { SrcBlock "C21" SrcPort 1 DstBlock "Logical\nOperator" DstPort 21 } Line { SrcBlock "C20" SrcPort 1 DstBlock "Logical\nOperator" DstPort 20 } Line { SrcBlock "C19" SrcPort 1 DstBlock "Logical\nOperator" DstPort 19 } Line { SrcBlock "C18" SrcPort 1 DstBlock "Logical\nOperator" DstPort 18 } Line { SrcBlock "C17" SrcPort 1 DstBlock "Logical\nOperator" DstPort 17 } Line { SrcBlock "C16" SrcPort 1 DstBlock "Logical\nOperator" DstPort 16 } Line { SrcBlock "C15" SrcPort 1 DstBlock "Logical\nOperator" DstPort 15 } Line { SrcBlock "C14" SrcPort 1 DstBlock "Logical\nOperator" DstPort 14 } Line { SrcBlock "C13" SrcPort 1 DstBlock "Logical\nOperator" DstPort 13 } Line { SrcBlock "C12" SrcPort 1 DstBlock "Logical\nOperator" DstPort 12 } Line { SrcBlock "C11" SrcPort 1 DstBlock "Logical\nOperator" DstPort 11 } Line { SrcBlock "C10" SrcPort 1 DstBlock "Logical\nOperator" DstPort 10 } Line { SrcBlock "C9" SrcPort 1 DstBlock "Logical\nOperator" DstPort 9 } Line { SrcBlock "C8" SrcPort 1 DstBlock "Logical\nOperator" DstPort 8 } Line { SrcBlock "C7" SrcPort 1 DstBlock "Logical\nOperator" DstPort 7 } Line { SrcBlock "C6" SrcPort 1 DstBlock "Logical\nOperator" DstPort 6 } Line { SrcBlock "C5" SrcPort 1 DstBlock "Logical\nOperator" DstPort 5 } Line { SrcBlock "C4" SrcPort 1 DstBlock "Logical\nOperator" DstPort 4 } Line { SrcBlock "C3" SrcPort 1 DstBlock "Logical\nOperator" DstPort 3 } Line { SrcBlock "Logical\nOperator" SrcPort 1 DstBlock "Integer Delay" DstPort 1 } Line { SrcBlock "C2" SrcPort 1 DstBlock "Logical\nOperator" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 DstBlock "Logical\nOperator" DstPort 1 } Line { SrcBlock "Integer Delay" SrcPort 1 DstBlock "Out" DstPort 1 } } } Block { BlockType Outport Name "Out" Position [245, 28, 275, 42] IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Block { BlockType Outport Name "Done" Position [495, 118, 525, 132] Port "2" IconDisplay "Port number" BusOutputAsStruct off OutDataType "fixdt(1,16,0)" OutScaling "[]" } Line { SrcBlock "C32" SrcPort 1 DstBlock "Or2" DstPort 32 } Line { SrcBlock "C31" SrcPort 1 DstBlock "Or2" DstPort 31 } Line { SrcBlock "C30" SrcPort 1 DstBlock "Or2" DstPort 30 } Line { SrcBlock "C29" SrcPort 1 DstBlock "Or2" DstPort 29 } Line { SrcBlock "C28" SrcPort 1 DstBlock "Or2" DstPort 28 } Line { SrcBlock "C27" SrcPort 1 DstBlock "Or2" DstPort 27 } Line { SrcBlock "C26" SrcPort 1 DstBlock "Or2" DstPort 26 } Line { SrcBlock "C25" SrcPort 1 DstBlock "Or2" DstPort 25 } Line { SrcBlock "C24" SrcPort 1 DstBlock "Or2" DstPort 24 } Line { SrcBlock "C23" SrcPort 1 DstBlock "Or2" DstPort 23 } Line { SrcBlock "C22" SrcPort 1 DstBlock "Or2" DstPort 22 } Line { SrcBlock "C21" SrcPort 1 DstBlock "Or2" DstPort 21 } Line { SrcBlock "C20" SrcPort 1 DstBlock "Or2" DstPort 20 } Line { SrcBlock "C19" SrcPort 1 DstBlock "Or2" DstPort 19 } Line { SrcBlock "C18" SrcPort 1 DstBlock "Or2" DstPort 18 } Line { SrcBlock "C17" SrcPort 1 DstBlock "Or2" DstPort 17 } Line { SrcBlock "C16" SrcPort 1 DstBlock "Or2" DstPort 16 } Line { SrcBlock "C15" SrcPort 1 DstBlock "Or2" DstPort 15 } Line { SrcBlock "C14" SrcPort 1 DstBlock "Or2" DstPort 14 } Line { SrcBlock "C13" SrcPort 1 DstBlock "Or2" DstPort 13 } Line { SrcBlock "C12" SrcPort 1 DstBlock "Or2" DstPort 12 } Line { SrcBlock "C11" SrcPort 1 DstBlock "Or2" DstPort 11 } Line { SrcBlock "C10" SrcPort 1 DstBlock "Or2" DstPort 10 } Line { SrcBlock "C9" SrcPort 1 DstBlock "Or2" DstPort 9 } Line { SrcBlock "C8" SrcPort 1 DstBlock "Or2" DstPort 8 } Line { SrcBlock "C7" SrcPort 1 DstBlock "Or2" DstPort 7 } Line { SrcBlock "C6" SrcPort 1 DstBlock "Or2" DstPort 6 } Line { SrcBlock "C5" SrcPort 1 DstBlock "Or2" DstPort 5 } Line { SrcBlock "C4" SrcPort 1 DstBlock "Or2" DstPort 4 } Line { SrcBlock "C3" SrcPort 1 DstBlock "Or2" DstPort 3 } Line { SrcBlock "C2" SrcPort 1 DstBlock "Or2" DstPort 2 } Line { SrcBlock "C1" SrcPort 1 DstBlock "Or2" DstPort 1 } Line { SrcBlock "Or1" SrcPort 1 DstBlock "Done" DstPort 1 } Line { SrcBlock "And3" SrcPort 1 Points [5, 0; 0, -20] DstBlock "Or1" DstPort 2 } Line { SrcBlock "And2" SrcPort 1 Points [5, 0; 0, 20] DstBlock "Or1" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 Points [245, 0; 0, -30] Branch { DstBlock "And3" DstPort 2 } Branch { Points [0, -55] DstBlock "And2" DstPort 2 } } Line { SrcBlock "Not1" SrcPort 1 DstBlock "And3" DstPort 1 } Line { SrcBlock "Buf1" SrcPort 1 DstBlock "And2" DstPort 1 } Line { SrcBlock "Or2" SrcPort 1 Points [35, 0; 0, -460; 15, 0] Branch { Points [0, 55] DstBlock "Not1" DstPort 1 } Branch { DstBlock "Buf1" DstPort 1 } Branch { Points [0, -50] DstBlock "Out" DstPort 1 } } } } Block { BlockType Outport Name "Output" Position [1855, 738, 1885, 752] IconDisplay "Port number" BusOutputAsStruct off } Block { BlockType Outport Name "Done" Position [1855, 1798, 1885, 1812] Port "2" IconDisplay "Port number" BusOutputAsStruct off } Line { SrcBlock "a_And31" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 32 } Line { SrcBlock "a_And30" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 31 } Line { SrcBlock "a_And29" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 30 } Line { SrcBlock "a_And28" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 29 } Line { SrcBlock "a_And31" SrcPort 2 Points [685, 0] DstBlock "And32" DstPort 32 } Line { SrcBlock "a_And30" SrcPort 2 Points [665, 0] DstBlock "And32" DstPort 31 } Line { SrcBlock "a_And29" SrcPort 2 Points [645, 0] DstBlock "And32" DstPort 30 } Line { SrcBlock "a_And28" SrcPort 2 Points [625, 0] DstBlock "And32" DstPort 29 } Line { SrcBlock "Decode32" SrcPort 32 Points [0, 2070] DstBlock "a_And31" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 31 Points [0, 2005] DstBlock "a_And30" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 30 Points [0, 1940] DstBlock "a_And29" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 29 Points [0, 1875] DstBlock "a_And28" DstPort 2 } Line { SrcBlock "In31" SrcPort 1 DstBlock "a_And31" DstPort 1 } Line { SrcBlock "In30" SrcPort 1 DstBlock "a_And30" DstPort 1 } Line { SrcBlock "In29" SrcPort 1 DstBlock "a_And29" DstPort 1 } Line { SrcBlock "In28" SrcPort 1 DstBlock "a_And28" DstPort 1 } Line { SrcBlock "Start" SrcPort 1 DstBlock "Decode32" DstPort 6 } Line { SrcBlock "SelectCode/5" SrcPort 1 DstBlock "Demux" DstPort 1 } Line { SrcBlock "Demux" SrcPort 5 DstBlock "Decode32" DstPort 5 } Line { SrcBlock "Demux" SrcPort 4 DstBlock "Decode32" DstPort 4 } Line { SrcBlock "Demux" SrcPort 3 DstBlock "Decode32" DstPort 3 } Line { SrcBlock "Demux" SrcPort 2 DstBlock "Decode32" DstPort 2 } Line { SrcBlock "Demux" SrcPort 1 DstBlock "Decode32" DstPort 1 } Line { SrcBlock "a_Or32" SrcPort 2 DstBlock "Done" DstPort 1 } Line { SrcBlock "a_Or32" SrcPort 1 DstBlock "Output" DstPort 1 } Line { SrcBlock "And32" SrcPort 1 Points [455, 0; 0, 2220; -100, 0] DstBlock "a_Or32" DstPort 33 } Line { SrcBlock "a_And27" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 28 } Line { SrcBlock "a_And26" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 27 } Line { SrcBlock "a_And25" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 26 } Line { SrcBlock "a_And24" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 25 } Line { SrcBlock "a_And23" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 24 } Line { SrcBlock "a_And22" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 23 } Line { SrcBlock "a_And21" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 22 } Line { SrcBlock "a_And20" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 21 } Line { SrcBlock "a_And19" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 20 } Line { SrcBlock "a_And18" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 19 } Line { SrcBlock "a_And17" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 18 } Line { SrcBlock "a_And16" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 17 } Line { SrcBlock "a_And15" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 16 } Line { SrcBlock "a_And14" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 15 } Line { SrcBlock "a_And13" SrcPort 1 DstBlock "a_Or32" DstPort 14 } Line { SrcBlock "a_And12" SrcPort 1 DstBlock "a_Or32" DstPort 13 } Line { SrcBlock "a_And11" SrcPort 1 DstBlock "a_Or32" DstPort 12 } Line { SrcBlock "a_And10" SrcPort 1 DstBlock "a_Or32" DstPort 11 } Line { SrcBlock "a_And9" SrcPort 1 DstBlock "a_Or32" DstPort 10 } Line { SrcBlock "a_And8" SrcPort 1 DstBlock "a_Or32" DstPort 9 } Line { SrcBlock "a_And7" SrcPort 1 DstBlock "a_Or32" DstPort 8 } Line { SrcBlock "a_And6" SrcPort 1 DstBlock "a_Or32" DstPort 7 } Line { SrcBlock "a_And5" SrcPort 1 DstBlock "a_Or32" DstPort 6 } Line { SrcBlock "a_And4" SrcPort 1 DstBlock "a_Or32" DstPort 5 } Line { SrcBlock "a_And3" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 4 } Line { SrcBlock "a_And2" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 3 } Line { SrcBlock "a_And1" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 2 } Line { SrcBlock "a_And0" SrcPort 1 Points [730, 0] DstBlock "a_Or32" DstPort 1 } Line { SrcBlock "a_And27" SrcPort 2 Points [605, 0] DstBlock "And32" DstPort 28 } Line { SrcBlock "a_And26" SrcPort 2 Points [585, 0] DstBlock "And32" DstPort 27 } Line { SrcBlock "a_And25" SrcPort 2 Points [565, 0] DstBlock "And32" DstPort 26 } Line { SrcBlock "a_And24" SrcPort 2 Points [545, 0] DstBlock "And32" DstPort 25 } Line { SrcBlock "a_And23" SrcPort 2 Points [525, 0] DstBlock "And32" DstPort 24 } Line { SrcBlock "a_And22" SrcPort 2 Points [505, 0] DstBlock "And32" DstPort 23 } Line { SrcBlock "a_And21" SrcPort 2 Points [485, 0] DstBlock "And32" DstPort 22 } Line { SrcBlock "a_And20" SrcPort 2 Points [465, 0] DstBlock "And32" DstPort 21 } Line { SrcBlock "a_And19" SrcPort 2 Points [445, 0] DstBlock "And32" DstPort 20 } Line { SrcBlock "a_And18" SrcPort 2 Points [425, 0] DstBlock "And32" DstPort 19 } Line { SrcBlock "a_And17" SrcPort 2 Points [405, 0] DstBlock "And32" DstPort 18 } Line { SrcBlock "a_And16" SrcPort 2 Points [385, 0] DstBlock "And32" DstPort 17 } Line { SrcBlock "a_And15" SrcPort 2 Points [365, 0] DstBlock "And32" DstPort 16 } Line { SrcBlock "a_And14" SrcPort 2 Points [345, 0] DstBlock "And32" DstPort 15 } Line { SrcBlock "a_And13" SrcPort 2 Points [325, 0] DstBlock "And32" DstPort 14 } Line { SrcBlock "a_And12" SrcPort 2 Points [305, 0] DstBlock "And32" DstPort 13 } Line { SrcBlock "a_And11" SrcPort 2 Points [285, 0] DstBlock "And32" DstPort 12 } Line { SrcBlock "a_And10" SrcPort 2 Points [265, 0] DstBlock "And32" DstPort 11 } Line { SrcBlock "a_And9" SrcPort 2 Points [245, 0] DstBlock "And32" DstPort 10 } Line { SrcBlock "a_And8" SrcPort 2 Points [225, 0] DstBlock "And32" DstPort 9 } Line { SrcBlock "a_And7" SrcPort 2 Points [205, 0] DstBlock "And32" DstPort 8 } Line { SrcBlock "a_And6" SrcPort 2 Points [185, 0] DstBlock "And32" DstPort 7 } Line { SrcBlock "a_And5" SrcPort 2 Points [165, 0] DstBlock "And32" DstPort 6 } Line { SrcBlock "a_And4" SrcPort 2 Points [145, 0] DstBlock "And32" DstPort 5 } Line { SrcBlock "a_And3" SrcPort 2 Points [125, 0] DstBlock "And32" DstPort 4 } Line { SrcBlock "a_And2" SrcPort 2 Points [105, 0] DstBlock "And32" DstPort 3 } Line { SrcBlock "a_And1" SrcPort 2 Points [85, 0] DstBlock "And32" DstPort 2 } Line { SrcBlock "a_And0" SrcPort 2 Points [65, 0] DstBlock "And32" DstPort 1 } Line { SrcBlock "Decode32" SrcPort 28 Points [0, 1810] DstBlock "a_And27" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 27 Points [0, 1745] DstBlock "a_And26" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 26 Points [0, 1680] DstBlock "a_And25" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 25 Points [0, 1610] DstBlock "a_And24" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 24 Points [0, 1545] DstBlock "a_And23" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 23 Points [0, 1480] DstBlock "a_And22" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 22 Points [0, 1415] DstBlock "a_And21" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 21 Points [0, 1350] DstBlock "a_And20" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 20 Points [0, 1285] DstBlock "a_And19" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 19 Points [0, 1220] DstBlock "a_And18" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 18 Points [0, 1155] DstBlock "a_And17" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 17 Points [0, 1090] DstBlock "a_And16" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 16 Points [0, 1025] DstBlock "a_And15" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 15 Points [0, 960] DstBlock "a_And14" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 14 Points [0, 890] DstBlock "a_And13" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 13 Points [0, 825] DstBlock "a_And12" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 12 Points [0, 760] DstBlock "a_And11" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 11 Points [0, 695] DstBlock "a_And10" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 10 Points [0, 630] DstBlock "a_And9" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 9 Points [0, 565] DstBlock "a_And8" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 8 Points [0, 500] DstBlock "a_And7" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 7 Points [0, 435] DstBlock "a_And6" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 6 Points [0, 370] DstBlock "a_And5" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 5 Points [0, 305] DstBlock "a_And4" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 4 Points [0, 245] DstBlock "a_And3" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 3 Points [0, 180] DstBlock "a_And2" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 2 Points [0, 120] DstBlock "a_And1" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 1 Points [0, 55] DstBlock "a_And0" DstPort 2 } Line { SrcBlock "Decode32" SrcPort 33 Points [0, 70] Branch { DstBlock "a_And0" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And1" DstPort 3 } Branch { Points [0, 60] Branch { DstBlock "a_And2" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And3" DstPort 3 } Branch { Points [0, 60] Branch { DstBlock "a_And4" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And5" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And6" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And7" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And8" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And9" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And10" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And11" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And12" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And13" DstPort 3 } Branch { Points [0, 70] Branch { DstBlock "a_And14" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And15" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And16" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And17" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And18" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And19" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And20" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And21" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And22" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And23" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And24" DstPort 3 } Branch { Points [0, 70] Branch { DstBlock "a_And25" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And26" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And27" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And28" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And29" DstPort 3 } Branch { Points [0, 65] Branch { DstBlock "a_And30" DstPort 3 } Branch { Points [0, 65] DstBlock "a_And31" DstPort 3 } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } } Line { SrcBlock "In27" SrcPort 1 DstBlock "a_And27" DstPort 1 } Line { SrcBlock "In26" SrcPort 1 DstBlock "a_And26" DstPort 1 } Line { SrcBlock "In25" SrcPort 1 DstBlock "a_And25" DstPort 1 } Line { SrcBlock "In24" SrcPort 1 DstBlock "a_And24" DstPort 1 } Line { SrcBlock "In23" SrcPort 1 DstBlock "a_And23" DstPort 1 } Line { SrcBlock "In22" SrcPort 1 DstBlock "a_And22" DstPort 1 } Line { SrcBlock "In21" SrcPort 1 DstBlock "a_And21" DstPort 1 } Line { SrcBlock "In20" SrcPort 1 DstBlock "a_And20" DstPort 1 } Line { SrcBlock "In19" SrcPort 1 DstBlock "a_And19" DstPort 1 } Line { SrcBlock "In18" SrcPort 1 DstBlock "a_And18" DstPort 1 } Line { SrcBlock "In17" SrcPort 1 DstBlock "a_And17" DstPort 1 } Line { SrcBlock "In16" SrcPort 1 DstBlock "a_And16" DstPort 1 } Line { SrcBlock "In15" SrcPort 1 DstBlock "a_And15" DstPort 1 } Line { SrcBlock "In14" SrcPort 1 DstBlock "a_And14" DstPort 1 } Line { SrcBlock "In13" SrcPort 1 DstBlock "a_And13" DstPort 1 } Line { SrcBlock "In12" SrcPort 1 DstBlock "a_And12" DstPort 1 } Line { SrcBlock "In11" SrcPort 1 DstBlock "a_And11" DstPort 1 } Line { SrcBlock "In10" SrcPort 1 DstBlock "a_And10" DstPort 1 } Line { SrcBlock "In9" SrcPort 1 DstBlock "a_And9" DstPort 1 } Line { SrcBlock "In8" SrcPort 1 DstBlock "a_And8" DstPort 1 } Line { SrcBlock "In7" SrcPort 1 DstBlock "a_And7" DstPort 1 } Line { SrcBlock "In6" SrcPort 1 DstBlock "a_And6" DstPort 1 } Line { SrcBlock "In5" SrcPort 1 DstBlock "a_And5" DstPort 1 } Line { SrcBlock "In4" SrcPort 1 DstBlock "a_And4" DstPort 1 } Line { SrcBlock "In3" SrcPort 1 DstBlock "a_And3" DstPort 1 } Line { SrcBlock "In2" SrcPort 1 DstBlock "a_And2" DstPort 1 } Line { SrcBlock "In1" SrcPort 1 DstBlock "a_And1" DstPort 1 } Line { SrcBlock "In0" SrcPort 1 DstBlock "a_And0" DstPort 1 } } }