Model {
  Name			  "peices"
  Version		  7.1
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.63"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "windows-1252"
  SaveDefaultBlockParams  on
  SampleTimeColors	  off
  LibraryLinkDisplay	  "none"
  WideLines		  off
  ShowLineDimensions	  off
  ShowPortDataTypes	  off
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  ShowStorageClass	  off
  ShowTestPointIcons	  on
  ShowSignalResolutionIcons on
  ShowViewerIcons	  on
  SortedOrder		  off
  ExecutionContextIcon	  off
  ShowLinearizationAnnotations on
  ScopeRefreshTime	  0.035000
  OverrideScopeRefreshTime on
  DisableAllScopes	  off
  DataTypeOverride	  "UseLocalSettings"
  MinMaxOverflowLogging	  "UseLocalSettings"
  MinMaxOverflowArchiveMode "Overwrite"
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks off
  BrowserLookUnderMasks	  off
  Created		  "Fri Nov 21 00:22:06 2008"
  Creator		  "ysun"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "ysun"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Tue Dec 09 13:45:03 2008"
  RTWModifiedTimeStamp	  0
  ModelVersionFormat	  "1.%<AutoIncrement:63>"
  ConfigurationManager	  "None"
  SimulationMode	  "normal"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  AccelSystemTargetFile	  "accel.tlc"
  AccelTemplateMakefile	  "accel_default_tmf"
  AccelMakeCommand	  "make_rtw"
  TryForcingSFcnDF	  off
  RecordCoverage	  off
  CovPath		  "/"
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeVarName	  "covCumulativeData"
  CovCumulativeReport	  off
  CovReportOnPause	  on
  CovModelRefEnable	  "Off"
  ExtModeBatchMode	  off
  ExtModeEnableFloating	  on
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigDurationFloating "auto"
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  BufferReuse		  on
  ShowModelReferenceBlockVersion off
  ShowModelReferenceBlockIO off
  Array {
    Type		    "Handle"
    Dimension		    1
    Simulink.ConfigSet {
      $ObjectID		      1
      Version		      "1.4.0"
      Array {
	Type			"Handle"
	Dimension		7
	Simulink.SolverCC {
	  $ObjectID		  2
	  Version		  "1.4.0"
	  StartTime		  "0.0"
	  StopTime		  "1000"
	  AbsTol		  "auto"
	  FixedStep		  ".1"
	  InitialStep		  "auto"
	  MaxNumMinSteps	  "-1"
	  MaxOrder		  5
	  ZcThreshold		  "auto"
	  ConsecutiveZCsStepRelTol "10*128*eps"
	  MaxConsecutiveZCs	  "1000"
	  ExtrapolationOrder	  4
	  NumberNewtonIterations  1
	  MaxStep		  "auto"
	  MinStep		  "auto"
	  MaxConsecutiveMinStep	  "1"
	  RelTol		  "1e-3"
	  SolverMode		  "Auto"
	  Solver		  "ode45"
	  SolverName		  "ode45"
	  ShapePreserveControl	  "DisableAll"
	  ZeroCrossControl	  "UseLocalSettings"
	  ZeroCrossAlgorithm	  "Non-adaptive"
	  AlgebraicLoopSolver	  "TrustRegion"
	  SolverResetMethod	  "Fast"
	  PositivePriorityOrder	  off
	  AutoInsertRateTranBlk	  off
	  SampleTimeConstraint	  "Unconstrained"
	  InsertRTBMode		  "Whenever possible"
	}
	Simulink.DataIOCC {
	  $ObjectID		  3
	  Version		  "1.4.0"
	  Decimation		  "1"
	  ExternalInput		  "[t, u]"
	  FinalStateName	  "xFinal"
	  InitialState		  "xInitial"
	  LimitDataPoints	  on
	  MaxDataPoints		  "1000"
	  LoadExternalInput	  off
	  LoadInitialState	  off
	  SaveFinalState	  off
	  SaveFormat		  "Array"
	  SaveOutput		  on
	  SaveState		  off
	  SignalLogging		  on
	  InspectSignalLogs	  off
	  SaveTime		  on
	  StateSaveName		  "xout"
	  TimeSaveName		  "tout"
	  OutputSaveName	  "yout"
	  SignalLoggingName	  "logsout"
	  OutputOption		  "RefineOutputTimes"
	  OutputTimes		  "[]"
	  Refine		  "1"
	}
	Simulink.OptimizationCC {
	  $ObjectID		  4
	  Array {
	    Type		    "Cell"
	    Dimension		    5
	    Cell		    "ZeroExternalMemoryAtStartup"
	    Cell		    "ZeroInternalMemoryAtStartup"
	    Cell		    "InitFltsAndDblsToZero"
	    Cell		    "OptimizeModelRefInitCode"
	    Cell		    "NoFixptDivByZeroProtection"
	    PropName		    "DisabledProps"
	  }
	  Version		  "1.4.0"
	  BlockReduction	  on
	  BooleanDataType	  on
	  ConditionallyExecuteInputs on
	  InlineParams		  off
	  InlineInvariantSignals  off
	  OptimizeBlockIOStorage  on
	  BufferReuse		  on
	  EnhancedBackFolding	  off
	  EnforceIntegerDowncast  on
	  ExpressionFolding	  on
	  ExpressionDepthLimit	  2147483647
	  FoldNonRolledExpr	  on
	  LocalBlockOutputs	  on
	  RollThreshold		  5
	  SystemCodeInlineAuto	  off
	  StateBitsets		  off
	  DataBitsets		  off
	  UseTempVars		  off
	  ZeroExternalMemoryAtStartup on
	  ZeroInternalMemoryAtStartup on
	  InitFltsAndDblsToZero	  on
	  NoFixptDivByZeroProtection off
	  EfficientFloat2IntCast  off
	  OptimizeModelRefInitCode off
	  LifeSpan		  "inf"
	  BufferReusableBoundary  on
	  SimCompilerOptimization "Off"
	  AccelVerboseBuild	  off
	}
	Simulink.DebuggingCC {
	  $ObjectID		  5
	  Version		  "1.4.0"
	  RTPrefix		  "error"
	  ConsistencyChecking	  "none"
	  ArrayBoundsChecking	  "none"
	  SignalInfNanChecking	  "none"
	  SignalRangeChecking	  "none"
	  ReadBeforeWriteMsg	  "UseLocalSettings"
	  WriteAfterWriteMsg	  "UseLocalSettings"
	  WriteAfterReadMsg	  "UseLocalSettings"
	  AlgebraicLoopMsg	  "warning"
	  ArtificialAlgebraicLoopMsg "warning"
	  SaveWithDisabledLinksMsg "warning"
	  SaveWithParameterizedLinksMsg	"none"
	  CheckSSInitialOutputMsg on
	  CheckExecutionContextPreStartOutputMsg off
	  CheckExecutionContextRuntimeOutputMsg	off
	  SignalResolutionControl "UseLocalSettings"
	  BlockPriorityViolationMsg "warning"
	  MinStepSizeMsg	  "warning"
	  TimeAdjustmentMsg	  "none"
	  MaxConsecutiveZCsMsg	  "error"
	  SolverPrmCheckMsg	  "warning"
	  InheritedTsInSrcMsg	  "warning"
	  DiscreteInheritContinuousMsg "warning"
	  MultiTaskDSMMsg	  "error"
	  MultiTaskCondExecSysMsg "error"
	  MultiTaskRateTransMsg	  "error"
	  SingleTaskRateTransMsg  "none"
	  TasksWithSamePriorityMsg "warning"
	  SigSpecEnsureSampleTimeMsg "warning"
	  CheckMatrixSingularityMsg "none"
	  IntegerOverflowMsg	  "warning"
	  Int32ToFloatConvMsg	  "warning"
	  ParameterDowncastMsg	  "error"
	  ParameterOverflowMsg	  "error"
	  ParameterUnderflowMsg	  "none"
	  ParameterPrecisionLossMsg "warning"
	  ParameterTunabilityLossMsg "warning"
	  UnderSpecifiedDataTypeMsg "none"
	  UnnecessaryDatatypeConvMsg "none"
	  VectorMatrixConversionMsg "none"
	  InvalidFcnCallConnMsg	  "error"
	  FcnCallInpInsideContextMsg "Use local settings"
	  SignalLabelMismatchMsg  "none"
	  UnconnectedInputMsg	  "warning"
	  UnconnectedOutputMsg	  "warning"
	  UnconnectedLineMsg	  "warning"
	  SFcnCompatibilityMsg	  "none"
	  UniqueDataStoreMsg	  "none"
	  BusObjectLabelMismatch  "warning"
	  RootOutportRequireBusObject "warning"
	  AssertControl		  "UseLocalSettings"
	  EnableOverflowDetection off
	  ModelReferenceIOMsg	  "none"
	  ModelReferenceVersionMismatchMessage "none"
	  ModelReferenceIOMismatchMessage "none"
	  ModelReferenceCSMismatchMessage "none"
	  ModelReferenceSimTargetVerbose off
	  UnknownTsInhSupMsg	  "warning"
	  ModelReferenceDataLoggingMessage "warning"
	  ModelReferenceSymbolNameMessage "warning"
	  ModelReferenceExtraNoncontSigs "error"
	  StateNameClashWarn	  "warning"
	  StrictBusMsg		  "Warning"
	  LoggingUnavailableSignals "error"
	  BlockIODiagnostic	  "none"
	}
	Simulink.HardwareCC {
	  $ObjectID		  6
	  Version		  "1.4.0"
	  ProdBitPerChar	  8
	  ProdBitPerShort	  16
	  ProdBitPerInt		  32
	  ProdBitPerLong	  32
	  ProdIntDivRoundTo	  "Undefined"
	  ProdEndianess		  "Unspecified"
	  ProdWordSize		  32
	  ProdShiftRightIntArith  on
	  ProdHWDeviceType	  "32-bit Generic"
	  TargetBitPerChar	  8
	  TargetBitPerShort	  16
	  TargetBitPerInt	  32
	  TargetBitPerLong	  32
	  TargetShiftRightIntArith on
	  TargetIntDivRoundTo	  "Undefined"
	  TargetEndianess	  "Unspecified"
	  TargetWordSize	  32
	  TargetTypeEmulationWarnSuppressLevel 0
	  TargetPreprocMaxBitsSint 32
	  TargetPreprocMaxBitsUint 32
	  TargetHWDeviceType	  "Specified"
	  TargetUnknown		  off
	  ProdEqTarget		  on
	}
	Simulink.ModelReferenceCC {
	  $ObjectID		  7
	  Version		  "1.4.0"
	  UpdateModelReferenceTargets "IfOutOfDateOrStructuralChange"
	  CheckModelReferenceTargetMessage "error"
	  ModelReferenceNumInstancesAllowed "Multi"
	  ModelReferenceSigSizeVariationType "Always allowed"
	  ModelReferencePassRootInputsByReference on
	  ModelReferenceMinAlgLoopOccurrences off
	}
	Simulink.RTWCC {
	  $BackupClass		  "Simulink.RTWCC"
	  $ObjectID		  8
	  Array {
	    Type		    "Cell"
	    Dimension		    6
	    Cell		    "IncludeHyperlinkInReport"
	    Cell		    "GenerateTraceInfo"
	    Cell		    "GenerateTraceReport"
	    Cell		    "GenerateTraceReportSl"
	    Cell		    "GenerateTraceReportSf"
	    Cell		    "GenerateTraceReportEml"
	    PropName		    "DisabledProps"
	  }
	  Version		  "1.4.0"
	  SystemTargetFile	  "grt.tlc"
	  GenCodeOnly		  off
	  MakeCommand		  "make_rtw"
	  GenerateMakefile	  on
	  TemplateMakefile	  "grt_default_tmf"
	  GenerateReport	  off
	  SaveLog		  off
	  RTWVerbose		  on
	  RetainRTWFile		  off
	  ProfileTLC		  off
	  TLCDebug		  off
	  TLCCoverage		  off
	  TLCAssert		  off
	  ProcessScriptMode	  "Default"
	  ConfigurationMode	  "Optimized"
	  ConfigAtBuild		  off
	  IncludeHyperlinkInReport off
	  LaunchReport		  off
	  TargetLang		  "C"
	  IncludeBusHierarchyInRTWFileBlockHierarchyMap	off
	  IncludeERTFirstTime	  off
	  GenerateTraceInfo	  off
	  GenerateTraceReport	  off
	  GenerateTraceReportSl	  off
	  GenerateTraceReportSf	  off
	  GenerateTraceReportEml  off
	  GenerateCodeInfo	  off
	  RTWCompilerOptimization "Off"
	  Array {
	    Type		    "Handle"
	    Dimension		    2
	    Simulink.CodeAppCC {
	      $ObjectID		      9
	      Array {
		Type			"Cell"
		Dimension		16
		Cell			"IgnoreCustomStorageClasses"
		Cell			"InsertBlockDesc"
		Cell			"SFDataObjDesc"
		Cell			"SimulinkDataObjDesc"
		Cell			"DefineNamingRule"
		Cell			"SignalNamingRule"
		Cell			"ParamNamingRule"
		Cell			"InlinedPrmAccess"
		Cell			"CustomSymbolStr"
		Cell			"CustomSymbolStrGlobalVar"
		Cell			"CustomSymbolStrType"
		Cell			"CustomSymbolStrField"
		Cell			"CustomSymbolStrFcn"
		Cell			"CustomSymbolStrBlkIO"
		Cell			"CustomSymbolStrTmpVar"
		Cell			"CustomSymbolStrMacro"
		PropName		"DisabledProps"
	      }
	      Version		      "1.4.0"
	      ForceParamTrailComments off
	      GenerateComments	      on
	      IgnoreCustomStorageClasses on
	      IncHierarchyInIds	      off
	      MaxIdLength	      31
	      PreserveName	      off
	      PreserveNameWithParent  off
	      ShowEliminatedStatement off
	      IncAutoGenComments      off
	      SimulinkDataObjDesc     off
	      SFDataObjDesc	      off
	      IncDataTypeInIds	      off
	      MangleLength	      1
	      CustomSymbolStrGlobalVar "$R$N$M"
	      CustomSymbolStrType     "$N$R$M"
	      CustomSymbolStrField    "$N$M"
	      CustomSymbolStrFcn      "$R$N$M$F"
	      CustomSymbolStrBlkIO    "rtb_$N$M"
	      CustomSymbolStrTmpVar   "$N$M"
	      CustomSymbolStrMacro    "$R$N$M"
	      DefineNamingRule	      "None"
	      ParamNamingRule	      "None"
	      SignalNamingRule	      "None"
	      InsertBlockDesc	      off
	      SimulinkBlockComments   on
	      EnableCustomComments    off
	      InlinedPrmAccess	      "Literals"
	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		16
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"GenerateTestInterfaces"
		Cell			"ModelStepFunctionPrototypeControlCompliant"
		Cell			"CPPClassGenCompliant"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		Cell			"PortableWordSizes"
		PropName		"DisabledProps"
	      }
	      Version		      "1.4.0"
	      TargetFcnLib	      "ansi_tfl_table_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      TargetFunctionLibrary   "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      GenerateTestInterfaces  off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      CompOptLevelCompliant   on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      ERTFirstTimeCompliant   off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      EnableShiftOperators    on
	      ParenthesesLevel	      "Nominal"
	      PortableWordSizes	      off
	      ModelStepFunctionPrototypeControlCompliant off
	      AutosarCompliant	      off
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      ExtModeIntrfLevel	      "Level1"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: auto"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Logic
      Operator		      "AND"
      Inputs		      "2"
      IconShape		      "rectangular"
      AllPortsSameDT	      on
      OutDataTypeMode	      "Logical (see Configuration Parameters: Optimization)"
      LogicDataType	      "uint(8)"
      OutDataTypeStr	      "Inherit: Logical (see Configuration Parameters: Optimization)"
      SampleTime	      "-1"
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: auto"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
      SFunctionDeploymentMode off
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      "FromPortIcon"
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      CheckFcnCallInpInsideContextMsg off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    UseDisplayTextAsClickCallback off
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "peices"
    Location		    [631, 122, 1052, 789]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "usletter"
    PaperUnits		    "inches"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      SubSystem
      Name		      "Asynchronous And"
      Ports		      [3, 2]
      Position		      [210, 130, 295, 180]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Asynchronous And"
	Location		[248, 461, 1028, 780]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [45, 38, 75, 52]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 178, 55, 192]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "s"
	  Position		  [390, 215, 420, 230]
	  Orientation		  "up"
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And1"
	  Ports			  [2, 1]
	  Position		  [145, 138, 230, 202]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And2"
	  Ports			  [2, 1]
	  Position		  [145, 28, 230, 92]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And3"
	  Ports			  [2, 1]
	  Position		  [440, 43, 525, 107]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And3"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And4"
	  Ports			  [2, 1]
	  Position		  [475, 153, 560, 217]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And4"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not2"
	  Ports			  [1, 1]
	  Position		  [305, 44, 390, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or2"
	  Ports			  [2, 1]
	  Position		  [610, 58, 695, 122]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [290, 213, 320, 227]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "f"
	  Position		  [715, 83, 745, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Realistic And2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Realistic And1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And2"
	  SrcPort		  1
	  DstBlock		  "Realistic Not2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic And1"
	  SrcPort		  1
	  Points		  [35, 0]
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "Out"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Realistic And4"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not2"
	  SrcPort		  1
	  DstBlock		  "Realistic And3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "s"
	  SrcPort		  1
	  Points		  [0, -10]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And3"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And4"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And4"
	  SrcPort		  1
	  Points		  [25, 0; 0, -80]
	  DstBlock		  "Realistic Or2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Realistic And3"
	  SrcPort		  1
	  DstBlock		  "Realistic Or2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Or2"
	  SrcPort		  1
	  DstBlock		  "f"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Asynchronous Nand"
      Ports		      [3, 2]
      Position		      [210, 372, 290, 428]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Asynchronous Nand"
	Location		[309, 429, 1089, 748]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [45, 38, 75, 52]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 178, 55, 192]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "s"
	  Position		  [385, 215, 415, 230]
	  Orientation		  "up"
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And1"
	  Ports			  [2, 1]
	  Position		  [475, 153, 560, 217]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And2"
	  Ports			  [2, 1]
	  Position		  [435, 43, 520, 107]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Nand1"
	  Ports			  [2, 1]
	  Position		  [145, 138, 230, 202]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Nand1"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "NAND"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Nand2"
	  Ports			  [2, 1]
	  Position		  [145, 28, 230, 92]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Nand2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "NAND"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not2"
	  Ports			  [1, 1]
	  Position		  [300, 44, 385, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or2"
	  Ports			  [2, 1]
	  Position		  [605, 58, 690, 122]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [285, 213, 315, 227]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "f"
	  Position		  [710, 83, 740, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Realistic Nand2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Realistic Nand1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic Nand2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic Nand1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic Nand2"
	  SrcPort		  1
	  DstBlock		  "Realistic Not2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Nand1"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "Out"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not2"
	  SrcPort		  1
	  DstBlock		  "Realistic And2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "s"
	  SrcPort		  1
	  Points		  [0, -10]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And1"
	  SrcPort		  1
	  Points		  [20, 0; 0, -80]
	  DstBlock		  "Realistic Or2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Realistic And2"
	  SrcPort		  1
	  DstBlock		  "Realistic Or2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Or2"
	  SrcPort		  1
	  DstBlock		  "f"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Asynchronous Nor"
      Ports		      [3, 2]
      Position		      [210, 208, 295, 262]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Asynchronous Nor"
	Location		[148, 485, 928, 804]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [45, 38, 75, 52]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 178, 55, 192]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "s"
	  Position		  [385, 215, 415, 230]
	  Orientation		  "up"
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And1"
	  Ports			  [2, 1]
	  Position		  [475, 153, 560, 217]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And2"
	  Ports			  [2, 1]
	  Position		  [435, 43, 520, 107]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Nor1"
	  Ports			  [2, 1]
	  Position		  [160, 138, 245, 202]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Nor1"
	    Location		    [550, 99, 924, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [255, 43, 290, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "NOR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Nor2"
	  Ports			  [2, 1]
	  Position		  [155, 28, 240, 92]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Nor2"
	    Location		    [550, 99, 924, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [255, 43, 290, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "NOR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not2"
	  Ports			  [1, 1]
	  Position		  [295, 44, 380, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or2"
	  Ports			  [2, 1]
	  Position		  [605, 58, 690, 122]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [285, 213, 315, 227]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "f"
	  Position		  [710, 83, 740, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Realistic Nor2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Realistic Nor1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic Nor2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic Nor1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic Nor2"
	  SrcPort		  1
	  DstBlock		  "Realistic Not2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Nor1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "Out"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not2"
	  SrcPort		  1
	  DstBlock		  "Realistic And2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "s"
	  SrcPort		  1
	  Points		  [0, -10]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And1"
	  SrcPort		  1
	  Points		  [20, 0; 0, -80]
	  DstBlock		  "Realistic Or2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Realistic And2"
	  SrcPort		  1
	  DstBlock		  "Realistic Or2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Or2"
	  SrcPort		  1
	  DstBlock		  "f"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Asynchronous Not"
      Ports		      [2, 2]
      Position		      [210, 458, 290, 502]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Asynchronous Not"
	Location		[330, 290, 1110, 609]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [45, 53, 75, 67]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "s"
	  Position		  [385, 215, 415, 230]
	  Orientation		  "up"
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And1"
	  Ports			  [2, 1]
	  Position		  [485, 153, 570, 217]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And2"
	  Ports			  [2, 1]
	  Position		  [430, 43, 515, 107]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not1"
	  Ports			  [1, 1]
	  Position		  [155, 149, 240, 181]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not1"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not2"
	  Ports			  [1, 1]
	  Position		  [150, 44, 235, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not3"
	  Ports			  [1, 1]
	  Position		  [300, 44, 385, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not3"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or2"
	  Ports			  [2, 1]
	  Position		  [600, 58, 685, 122]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [285, 213, 315, 227]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "f"
	  Position		  [710, 83, 740, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Realistic Not2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 105]
	    DstBlock		    "Realistic Not1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not2"
	  SrcPort		  1
	  DstBlock		  "Realistic Not3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Not1"
	  SrcPort		  1
	  Points		  [20, 0]
	  Branch {
	    Points		    [0, 55]
	    DstBlock		    "Out"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [205, 0]
	    DstBlock		    "Realistic And1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not3"
	  SrcPort		  1
	  DstBlock		  "Realistic And2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "s"
	  SrcPort		  1
	  Points		  [0, -10]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And1"
	  SrcPort		  1
	  Points		  [10, 0]
	  DstBlock		  "Realistic Or2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Realistic And2"
	  SrcPort		  1
	  DstBlock		  "Realistic Or2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Or2"
	  SrcPort		  1
	  DstBlock		  "f"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Asynchronous Or"
      Ports		      [3, 2]
      Position		      [210, 42, 295, 98]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Asynchronous Or"
	Location		[372, 440, 1152, 725]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [45, 38, 75, 52]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 178, 55, 192]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "s"
	  Position		  [385, 215, 415, 230]
	  Orientation		  "up"
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And1"
	  Ports			  [2, 1]
	  Position		  [470, 153, 555, 217]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And2"
	  Ports			  [2, 1]
	  Position		  [435, 43, 520, 107]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not2"
	  Ports			  [1, 1]
	  Position		  [295, 44, 380, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or1"
	  Ports			  [2, 1]
	  Position		  [145, 138, 230, 202]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or2"
	  Ports			  [2, 1]
	  Position		  [145, 28, 230, 92]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or3"
	  Ports			  [2, 1]
	  Position		  [600, 58, 685, 122]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or3"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [285, 213, 315, 227]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "f"
	  Position		  [710, 83, 740, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "Realistic Or2"
	  SrcPort		  1
	  DstBlock		  "Realistic Not2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Realistic Or2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Realistic Or1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic Or2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic Or1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic Or1"
	  SrcPort		  1
	  Points		  [30, 0]
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "Out"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not2"
	  SrcPort		  1
	  DstBlock		  "Realistic And2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "s"
	  SrcPort		  1
	  Points		  [0, -10]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And1"
	  SrcPort		  1
	  Points		  [25, 0]
	  DstBlock		  "Realistic Or3"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Realistic And2"
	  SrcPort		  1
	  DstBlock		  "Realistic Or3"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Or3"
	  SrcPort		  1
	  DstBlock		  "f"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Asynchronous Xor"
      Ports		      [3, 2]
      Position		      [210, 292, 295, 348]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Asynchronous Xor"
	Location		[178, 429, 958, 748]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [45, 38, 75, 52]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 178, 55, 192]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "s"
	  Position		  [380, 215, 410, 230]
	  Orientation		  "up"
	  Port			  "3"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And1"
	  Ports			  [2, 1]
	  Position		  [470, 153, 555, 217]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And1"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic And2"
	  Ports			  [2, 1]
	  Position		  [430, 43, 515, 107]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic And2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [265, 43, 300, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Not2"
	  Ports			  [1, 1]
	  Position		  [295, 44, 380, 76]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Not2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [80, 44, 110, 76]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      Points		      [5, 0]
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Or2"
	  Ports			  [2, 1]
	  Position		  [600, 58, 685, 122]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Or2"
	    Location		    [532, 397, 907, 503]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [260, 43, 295, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "OR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Xor1"
	  Ports			  [2, 1]
	  Position		  [145, 138, 230, 202]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Xor1"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [255, 43, 290, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "XOR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Realistic Xor2"
	  Ports			  [2, 1]
	  Position		  [145, 28, 230, 92]
	  MinAlgLoopOccurrences	  off
	  PropExecContextOutsideSubsystem off
	  RTWSystemCode		  "Auto"
	  FunctionWithSeparateData off
	  Opaque		  off
	  RequestExecContextInheritance	off
	  MaskHideContents	  off
	  System {
	    Name		    "Realistic Xor2"
	    Location		    [550, 99, 925, 205]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
	    TiledPageScale	    1
	    ShowPageBoundaries	    off
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [25, 43, 55, 57]
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "In2"
	      Position		      [25, 58, 55, 72]
	      Port		      "2"
	      IconDisplay	      "Port number"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "Integer Delay"
	      Ports		      [1, 1]
	      Position		      [255, 43, 290, 77]
	      SourceBlock	      "simulink/Discrete/Integer Delay"
	      SourceType	      "Integer Delay"
	      vinit		      "0.0"
	      samptime		      "-1"
	      NumDelays		      "delay"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [2, 1]
	      Position		      [80, 42, 110, 73]
	      NamePlacement	      "alternate"
	      Operator		      "XOR"
	      AllPortsSameDT	      off
	      OutDataTypeMode	      "boolean"
	      OutDataTypeStr	      "boolean"
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [320, 53, 350, 67]
	      IconDisplay	      "Port number"
	    }
	    Line {
	      SrcBlock		      "In2"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      2
	    }
	    Line {
	      SrcBlock		      "Integer Delay"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Integer Delay"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out"
	  Position		  [280, 213, 310, 227]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Outport
	  Name			  "f"
	  Position		  [705, 83, 735, 97]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    DstBlock		    "Realistic Xor2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, 110]
	    DstBlock		    "Realistic Xor1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  Points		  [15, 0]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic Xor2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic Xor1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic Xor2"
	  SrcPort		  1
	  DstBlock		  "Realistic Not2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Xor1"
	  SrcPort		  1
	  Points		  [25, 0]
	  Branch {
	    Points		    [0, 50]
	    DstBlock		    "Out"
	    DstPort		    1
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "Realistic Not2"
	  SrcPort		  1
	  DstBlock		  "Realistic And2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "s"
	  SrcPort		  1
	  Points		  [0, -10]
	  Branch {
	    Points		    [0, -110]
	    DstBlock		    "Realistic And2"
	    DstPort		    2
	  }
	  Branch {
	    DstBlock		    "Realistic And1"
	    DstPort		    2
	  }
	}
	Line {
	  SrcBlock		  "Realistic And1"
	  SrcPort		  1
	  Points		  [20, 0; 0, -80]
	  DstBlock		  "Realistic Or2"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Realistic And2"
	  SrcPort		  1
	  DstBlock		  "Realistic Or2"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Realistic Or2"
	  SrcPort		  1
	  DstBlock		  "f"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Realistic And2"
      Ports		      [2, 1]
      Position		      [65, 116, 120, 149]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Realistic And2"
	Location		[303, 310, 678, 416]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 58, 55, 72]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Integer Delay"
	  Ports			  [1, 1]
	  Position		  [170, 43, 205, 77]
	  SourceBlock		  "simulink/Discrete/Integer Delay"
	  SourceType		  "Integer Delay"
	  vinit			  "0.0"
	  samptime		  "-1"
	  NumDelays		  "delay"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 42, 110, 73]
	  NamePlacement		  "alternate"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "boolean"
	  OutDataTypeStr	  "boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [225, 53, 255, 67]
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integer Delay"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Integer Delay"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Realistic Nand2"
      Ports		      [2, 1]
      Position		      [65, 310, 125, 345]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Realistic Nand2"
	Location		[550, 99, 925, 205]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 58, 55, 72]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Integer Delay"
	  Ports			  [1, 1]
	  Position		  [260, 43, 295, 77]
	  SourceBlock		  "simulink/Discrete/Integer Delay"
	  SourceType		  "Integer Delay"
	  vinit			  "0.0"
	  samptime		  "-1"
	  NumDelays		  "delay"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 42, 110, 73]
	  NamePlacement		  "alternate"
	  Operator		  "NAND"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "boolean"
	  OutDataTypeStr	  "boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [320, 53, 350, 67]
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integer Delay"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Integer Delay"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Realistic Nor2"
      Ports		      [2, 1]
      Position		      [65, 180, 120, 215]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Realistic Nor2"
	Location		[550, 99, 924, 205]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 58, 55, 72]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Integer Delay"
	  Ports			  [1, 1]
	  Position		  [255, 43, 290, 77]
	  SourceBlock		  "simulink/Discrete/Integer Delay"
	  SourceType		  "Integer Delay"
	  vinit			  "0.0"
	  samptime		  "-1"
	  NumDelays		  "delay"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 42, 110, 73]
	  NamePlacement		  "alternate"
	  Operator		  "NOR"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "boolean"
	  OutDataTypeStr	  "boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [320, 53, 350, 67]
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integer Delay"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Integer Delay"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Realistic Not2"
      Ports		      [1, 1]
      Position		      [70, 378, 120, 402]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Realistic Not2"
	Location		[550, 99, 925, 205]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Integer Delay"
	  Ports			  [1, 1]
	  Position		  [260, 43, 295, 77]
	  SourceBlock		  "simulink/Discrete/Integer Delay"
	  SourceType		  "Integer Delay"
	  vinit			  "0.0"
	  samptime		  "-1"
	  NumDelays		  "delay"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [1, 1]
	  Position		  [80, 44, 110, 76]
	  NamePlacement		  "alternate"
	  Operator		  "NOT"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "boolean"
	  OutDataTypeStr	  "boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [320, 53, 350, 67]
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  Points		  [5, 0]
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integer Delay"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Integer Delay"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Realistic Or2"
      Ports		      [2, 1]
      Position		      [65, 50, 120, 85]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Realistic Or2"
	Location		[114, 342, 489, 448]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 58, 55, 72]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Integer Delay"
	  Ports			  [1, 1]
	  Position		  [160, 43, 195, 77]
	  SourceBlock		  "simulink/Discrete/Integer Delay"
	  SourceType		  "Integer Delay"
	  vinit			  "0.0"
	  samptime		  "-1"
	  NumDelays		  "delay"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 42, 110, 73]
	  NamePlacement		  "alternate"
	  Operator		  "OR"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "boolean"
	  OutDataTypeStr	  "boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [220, 53, 250, 67]
	  IconDisplay		  "Port number"
	}
	Line {
	  Labels		  [1, 0]
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Integer Delay"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integer Delay"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  2
	}
      }
    }
    Block {
      BlockType		      SubSystem
      Name		      "Realistic Xor2"
      Ports		      [2, 1]
      Position		      [65, 240, 125, 275]
      MinAlgLoopOccurrences   off
      PropExecContextOutsideSubsystem off
      RTWSystemCode	      "Auto"
      FunctionWithSeparateData off
      Opaque		      off
      RequestExecContextInheritance off
      MaskHideContents	      off
      System {
	Name			"Realistic Xor2"
	Location		[550, 99, 925, 205]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	TiledPaperMargins	[0.500000, 0.500000, 0.500000, 0.500000]
	TiledPageScale		1
	ShowPageBoundaries	off
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "In1"
	  Position		  [25, 43, 55, 57]
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In2"
	  Position		  [25, 58, 55, 72]
	  Port			  "2"
	  IconDisplay		  "Port number"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Integer Delay"
	  Ports			  [1, 1]
	  Position		  [255, 43, 290, 77]
	  SourceBlock		  "simulink/Discrete/Integer Delay"
	  SourceType		  "Integer Delay"
	  vinit			  "0.0"
	  samptime		  "-1"
	  NumDelays		  "delay"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [2, 1]
	  Position		  [80, 42, 110, 73]
	  NamePlacement		  "alternate"
	  Operator		  "XOR"
	  AllPortsSameDT	  off
	  OutDataTypeMode	  "boolean"
	  OutDataTypeStr	  "boolean"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [320, 53, 350, 67]
	  IconDisplay		  "Port number"
	}
	Line {
	  SrcBlock		  "In1"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Integer Delay"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "In2"
	  SrcPort		  1
	  DstBlock		  "Logical\nOperator"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "Integer Delay"
	  DstPort		  1
	}
      }
    }
  }
}
# Finite State Machines
#
#    Stateflow Version 7.1 (R2008a) dated Feb  7 2008, 21:38:28
#
#


Stateflow {
  machine {
    id			    1
    name		    "peices"
    created		    "21-Nov-2008 00:45:16"
    isLibrary		    0
    firstTarget		    2
    sfVersion		    71014000.000003
  }
  target {
    id			    2
    name		    "sfun"
    description		    "Default Simulink S-Function Target."
    machine		    1
    linkNode		    [1 0 0]
  }
}