`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:55:40 12/01/2007 
// Design Name: 
// Module Name:    blink 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module blink(
        input clk,
        input i_reset,
        output [7:0] o_leds);

        reg [31:0] counter;
        assign o_leds = counter[31:24];
        
        always @ (posedge i_reset or posedge clk)
        begin
                if( i_reset ) counter <= 32'h0;
                else counter <= counter + 1'b1;
        end
        
endmodule