We're currently working on building a pipeline processor. Almost all the verilog is done, but there are some small gaps that need to be filled in. Once that's done, we'll need to add in some of the instructions the basic pipeline processor was missing (like bne, and some others I forget right now).

Once the pipeline processor is done, we'll be moving on to designing a vector arithmatic unit. We'll learn more about the design of other popular vector units (eg Altivec, MMX) and implement some reasonable set of pipeline features and instructions.

Vector Unit Links

• All my links on the subject are here: http://del.icio.us/heresiarch/VectorUnitDesign