The PowerPC Processor

Alex Dorsk, Katie Rivard, Nick Zola

Deliverables

• Presentation
• Paper

Timeline

• Day	Date	Due	Plan
  Mon	12/6	RESEARCH 80% DONE	Meet in class and compare notes
  Weds	12/8	RESEARCH 95% DONE	Create presentation outline, paper outline, divide up sections
  Mon	12/13	PAPER SECTIONS DONE	Group edits. Presenation bits done if possible
  Weds	12/15	PRESENTATION DONE	Group edits. Rehearse presentation.
  Thurs	12/16	EVERYTHING DONE	Give presentation.

Topics

• === History ===
  • IBM, 32bit, 64bit, altivec, caching, etc, other "revolutionary" features

  • /PowerPcArchitectureHistory

  === Architecture ===
  • Focus on differences

  • /PowerPcArchitectureArchitecture

  • IBM documentation for everything [here http://www-306.ibm.com/chips/techlib/techlib.nsf/productfamilies/PowerPC]:

  • /InstructionSet Notes from IBM .pdf e-manuals on PowerPC Instruction Set

  === Compare and Contrast ===
  • MIPS
  • Do some benchmarking -- write good Altivec code or dl somebody else's

Sources

• Ars Technica (Katie)

• IBM (Alex)

• Apple (Nick)

• CA text (everyone)

Notes

• === CA text ===

  • Bibliographical Information: Hennessy, John L. and David A. Patterson. Computer Organization and Design: The Hardware/Software Interface. 2nd ed. Morgan Kaufmann Publishers, Inc. San Francisco, CA. 1998.

  • 3.12: "Real Stuff: PowerPC and 80x86 Instructions" - PPC have some extended/collapsed instructions, as follows:
    • Indexed Addressing: Can address a section of memory as a sum of two registers directly

      • MIPS
         add  $t0, $a0, $s3
         lw   $t1, 0($t0)
        PPC
         lw   $t1, $a0+$s3

    • Update Addressing: Can do the load and increment the counter at the same time

      • MIPS
         lw    $t0, 4($s3)
         addi $s3, $s3, 4
        PPC
         lwu  $t0, 4($s3)

    • Load / Store multiple: can transfer up to 32 words of memory at once. For making fast copies w/in memory.

    • Looping: has a counter register specifically meant for loops. A bit restrictive, but hey, if it's useful...

      • MIPS
         Loop: ...
          addi $t0, $t0, -1
          bne  $t0, $zero, Loop
        PPC
          bc   Loop, $ctr!=0

  • 4.9: "Real Stuff: Floating Point in the PowerPC and 80x86"

    • fused multiply-add -- doesn't round until after the combined operation is complete. Highly accurate, esp for doing division.

  • 6.9: "Real Stuff: PowerPC and Pentium Pipelines"
    • Dynamically scheduled pipeline: fetches 16 bytes of instructions(ie, 4) from cache
    • Commit unit: sets validity/invalidity of an instruction "in progress" in the pipeline according to branch prediction
    • Very similar pipeline to Pentium Pro
    • Reorder buffer?

  === ArsTechnica ===

  • Stokes, Jon. "PowerPC on Apple: An Architectural History" Pt I. ars technica. Online. Available Dec 2004 http://arstechnica.com/articles/paedia/cpu/ppc-1.ars/1

    • PowerPcArchitectureHistory: POWER thru 604e

    • References, I:

      • PPC Compiler Writer's Guide

      • PPC 601 Whitepaper (IBM)

      • PPC 603 Whitepaper (IBM)

      • G1: The first generation (Mackido)

      • G2: The sequel (Mackido)

      • PPC Past and Present (Low End Mac)

      • What versions of the PPC are available? (Amiga History Guide)

      • Apples Power Failure (Realworldtech.com)

  • Stokes, Jon. "PowerPC on Apple: An Architectural History" Pt II. ars technica. Online. Available Dec 2004 http://arstechnica.com/articles/paedia/cpu/ppc-2.ars/1

    • /PowerPcArchitectureHistory: 750 thru 7450

  • Stokes, Jon. "Inside the IBM PowerPC 970 Pt I: Design Philosophy and Front End". ars technica. Online. 28 Oct 2002. Available Dec 2004 http://arstechnica.com/cpu/02q2/ppc970/ppc970-1.html

  • Stokes, Jon. "Inside the PowerPC 970 Part II: The Execution Core" ars technica. Online. 14 May 2003. Available Dec 2004 http://arstechnica.com/cpu/03q1/ppc970/ppc970-1.html