Some of the projects made web pages. Here they are: http://ca.olin.edu/2005/
Structure
- You can have any number of people on your group.
- You may extend your current CPU to add functionality or change architecture. For example, making it a pipelined CPU instead of a single-cycle CPU. Adding a vector calculation unit.
- Your team defines the goals, deliverables, and the timeline.
Groups
Public Key Cryptanalyzer -DJ Gallagher
- Public-key encryption schemes like RSA depend on the hardness of factoring large integers. Increasingly sophisticated algorithms have greatly reduced the computing cost, but the hardware needed to capitalize on them is sophisticated (it took 80 AMD Opterons to break RSA-200). I'm doing a proof-of-concept design (modeled at a much higher level than verilog) of a system based on very large networks of very simple devices that factor RSA keys by brute force. Such networks could be much more populous, and still cost less money to build.
Asynchronous FPGAs - Jon Tse, Mel Chua, Doug Ellwenger
- Description to follow
Cryptosystems/Encryption Hardware - Michael Wu, JJ Freeman, Kristen Dorsey
DSPs vs FPGAs - Joe College, Chris Doyle, Ann Marie Rynning
- We're looking into DSPs vs. FPGAs (literature review), and hope to make some comparisons in structure and function, and overview comments as to which solutions are more appropriate for certain types of applications. At this point, we're looking at doing a presentation on the last day of class. We will also be designing a website that covers this information.
Fuzzy Graph - Eric Gallimore, Nate Smith
We are implementing an algorithm for calculating escape time graphs of self-referential fuzzy logic equations. Its mathematical basis and implementation are described in a Powerpoint presentation available at http://students.olin.edu/2007/nsmith/portfolio/fuzzygraphs.ppt. Since it can take up to a minute to calculate a full-screen image with the current software based approach, we will be creating a custom processor with an FPGA to allow us to calculate graphs fast enough to use them in a real-time music visualizer.
Game of Life - Zach Brock, Nate Karst, Mike Siripong
- Specifically, we'd like to implement the computational aspect of the game through our CPU. Another possibility is writing a Verilog module to act as a single cell in the automata and implementing a net of these modules. We will research cellular automata in general and investigate the rich dynamics they produce in the particular example of the Game of Life.
Game of...game - [GameWiki] Mikell Taylor, Sean McBride, Brendan Doms, Brian Shih
- We will investigate and write an in depth discussion on how old arcade games were implemented in hardware and how it is possible to replicate them with FPGAs. We will then implement an existing arcade game on an FPGA (that has already been ported) and investigate how and why it works. Time permitting, we will also try and port a new game of our own.
High Availability Computing - Matt Colyer
- I am looking to do brief literature review of how high availablity services are designed for networks with rapidly changing peers. I intend to use the information I gather from the review in order to create a high availability service which allows clients to message each other using Python with a simple replication system. I plan on the deliverable being the implementation and a web site which explains the research I reviewed and how it affected the implementation I created. The deliverable will be completed on 12/13/2005.
Trinary logic - Ben Hill, Rob Nix, Madge Dodson
- We are going to investigate trinary logic for our final project. It will probably be mostly a survey type project with a paper/presentation deliverable, but we might also simulate a trinary CPU in a higher level language.
Water-Based Logic - Andrew Bouchard
- I'll be doing the water-based CPU, and I've already started work on the gates. I think that a reasonable goal would be to have an ALU done, perhaps up to about 5 bits. I'll also probably be talking to my grandfather, who was a civil engineer, about it over the break. I'd like to simulate the gates as close to reality as possible, meaning that the water that comes in is not the water that comes out. Basically, the idea is that the input water triggers some kind of switch that releases other water if a 1, and nothing if a zero.
More Water-Based Logic - Mark Penner
- The goal of this is to have a working 4x4 register file. It will maintain the values until the water is turned off.
Computer Arithmetic as it Relates to Computer Architecture - Cathy Murphie
- I will be writing a deliverable to take the form of a report, survey, or pseudo-textbook. Three possible veins for emphasis include the following: (1) comparison of various arithmetic architectures as relating to speed and ease of use; (2) development of a new arithmetic architecture scheme and analysis of its benefits; or (3) survey of the development of computer arithmetic as it evolves to become faster, more efficient, and more complex. A number of primary and secondary sources have already been compiled.
Links
- FPGA stuff
FPGA Development software (local mirror)
Spartan-3 Board - The FPGA board we have
- We have other boards, but they are sufficiently more complicated that this should be where you start. If you need more resources, let me know ASAP.
Video tutorials - For the Xilinx software/hardware we have
- Digital logic in water stuff
Ideas
- Cryptanalysis / Encryption hardware
CAD tools for CPU design (one that Mark has: http://www.tensilica.com/)
- FPGA emulator for arcade games
- DSP + FPGA literature review
- Comparison of different processors
- Build a CPU with water and/or LEGOS
- Asynchronous Logic for FPGAs and CPUs
- Game console architecture survey
- Power consumption and conservation
- High availability networked/distributed systems
- The IBM/Toshiba Cell Processor
- Trinary Computing
- Fixed point neural network
- The game of life - cellular automata
- Cellular automata + FPGAs
- Self configuring / self-repairing architectures