- WHO
Mark L. Chang (mark.chang at olin dot edu), TA: JoeCollege
- WHAT
- Computer Architecture!
- WHEN
- TF 10-11AM, W 9-11AM
- WHERE
- AC 304
- WHY
- Because ECEs have to. Because you couldn't think of a better class to take, otherwise.
- Communications
ca@lists.olin.edu, newsgroup: olin.courses.comparch (see http://acl.olin.edu/aclwiki/OlinNewsGroups)
- Office Hours
- By appointment.
- Text
Patterson, Hennessy, Computer Organization and Design: The Hardware/Software Interface, Third Edition, 2004, Morgan Kaufmann. Amazon Link. Samir Palnitkar’s Verilog HDL: A Guide to Digital Design and Synthesis is also recommended but not required.
Both texts are on reserve. The Patterson and Hennesey is on sale at Amazon right now for $52.
- Prerequisites
- Engineering, Math, and Physics Foundation. Programming background strongly recommended.
- Topics Covered
- Introduction to computer architecture, algorithms, hardware design for various computer subsystems, CPU control unit design, memory organization, cache design, and virtual memory.
- Assignments
- The major goals of the class are to familiarize you with basic structure of microprocessors. As part of this, students will develop a Verilog implementation of a simple RISC microprocessor based upon the MIPS instruction set.
- Exams
- There will be one midterm and one final exam.
- Attendance
- At your own risk :).
- Laptop Use
- Students are welcome to use laptops in class so long as it is not distracting.
- Outline
- The class will have the following approximate schedule. Material may be added or dropped based on class timing and progress.
- Introduction to processor architecture. Performance measures.
- Assembly language programming.
- Computer Arithmetic.
Processor Datapaths & Control.
- Pipelining.
- Memory hierarchy, caches, virtual memory.
- Advanced topics in computer architecture.
- Objectives
- By the end of the course, students should be able to:
- design, build, and simulate a working processor
- write programs in assembly and machine code
- describe complex hardware systems in Verilog
- analyze, comprehend, and critique commercial and research processors
- research and give an oral presentation on an advanced topic in the field of computer architecture
- analyze and calculate the tradeoffs of implementing optimizations
- Collaboration
- Groups of 2-3 for labs, individual for homework. For any other assignments, details will be given.
- For the labs the intention is to work primarily with your partners. If you run into problems, discussion with your classmates is fine. If you use classmates outside of your group, please note who they are on your submissions. I am also readily available to answer questions.
- For homework, the intention is to work primarily alone. If you are stuck, or need help, discussion with your classmates is fine. Again, please annotate who you collaborated with on a per-problem basis. I am happy to take any questions regarding homework in my office, or via email.
- The design of this policy requires good self-monitoring. If you are constantly relying on others to help you through the problems, there is something amiss. The collaboration policy is designed to foster discussion and group learning.