Contents
Current Projects
FPGA for blob tracking
Quantum Computing
Read Nielson & Chuang, some papers
- MATLAB (or possibly some specialized simulation environment) simulations: basic quantum gates, an algorithm
- Poster/paper/both
Sub-threshold computing
- General plan:
- Read 3 - 4 papers, mini lit survey
- "Cute circuits"
- Look up existing ones and do some simulation work
- Compare a sub-threshold circuit that does task A with a digital counterpart, in terms of power consumption, etc.
- Final deliverable will be poster and/or paper
Python bytecode machine
- Like picojava or lavacore for Python (ben)
- Pipelined processor with more MIPS instructions and maybe an FPU (ben)
- n-bit pipelined processor - ben
Target: Full Pipelined n-bit MIPS Processor in Verilisp
- Expectation: Pipelined n-bit Processor in Verilisp with most MIPS instructions
- Vector:
- sketch a pipelined processor in detail
- chart the cloud
- finish the rough patches of verilisp
- bring everything together in one concise verilisp file, which will generate pretty but verbose verilog
- documentation
Computation using the game of life
FPGA Coprocessor
JohnMorgan and DucNguyen
- Get Proto Boards
- Implement ATA
- Determine Application
- Implement Circuit
- Implement Host Software (Driver/Control)
K'NEX Computer
http://knexcomputer.blogspot.com/
- Maximal Deliverable - A full 8-bit CPU out of K'NEX
- Minimal Deliverable - A full set of parts and design of interconnects required to build a full 8-bit CPU
- Design Path - 1) Design all parts, 2) Build all parts, 3) Connect parts
FPGA Video Processing
- Real-time video effects, including bluescreen, overlay, and blur
- Final deliverable is a demo of the working system outputting to VGA
FPGA Compander
- Goal: FPGA that performs companding(~log(abs(x)) and un-companding(~exp(x)) in real time on voice signal
- Process:
- Research methods for performing necessary transforms
- Evaluate system requirements and choose best methods to implement
- Implement transforms on FPGA through Verilog
Integrate into system (from AnalDig project)
- Deliverables:
- Source verilog
- Working (hopefully) system
- Lab notebook documenting my work plus final summary document
Neural Networks
AnneItsuno, RobQuimby, JonPollack
- Maximal Deliverable - working program as an example of a neural network in addition to minimal deliverable.
- Minimal Deliverable - written report or tutorial covering general neural networks, algorithms,etc., and narrowed, in-depth coverage of one aspect of neural networks that we will decide within the next week.
Game of Life on FPGA
GeorgeHarris, StephenLongfield, JamesWhong
- Goal: Game of Life implemented on an FPGA with VGA output and mouse input for starting conditions.
- Minimum Deliverable: Documented code, working demo of Game of Life with VGA output.
- Todo: Get FPGA, VGA interface, write verilog, ???, profit
Audio wave-based processor
ChrisDellin, ScottMcClure, NickHays, JoeRoskowski
- Maximal Deliverable - fully functioning processor or Verilog translator that does computation using physical wave properties (constructive/destructive interference, beat frequencies, etc) using sound or water waves.
- Minimal Deliverable - device which uses said wave properties to do computation with a few gates (an adder, for example)
- Vector:
- Get physical wave properties working (assemble materials, test)
- Write code to control/decode the device
Project Ideas
- FPGA's that fight (and evolve) (robotic velociraptors)
- Asynchronous FPGAs
- Design and enhance CPU
- Build pipelined CPU
- Build branch predictor
- Altivec (vector processing unit)
- Real-time visual/video effects processor
- Real-time audio effects processor
- FPGA music visualizer
- Game of life in hardware
- Massively parallel computing environment from tiny CPUs on FPGA
- Genetic algorithms or Evolutionary computing
- MEMS based storage elements
- Adiabatic switching