Assume that all gates have a constant delay constant of 1 unit.
For each of the equations in Section 1 of Homework 1:
- Draw the circuit in gates as given
- Find the maximum input to output delay
- Simplify the using K-Maps or Boolean Laws, and draw the newly updated circuit
- Find the maximum input to output delay for your optimized version
Draw timing diagrams for a Gated SR Latch and a Gated D Latch. Try using only NANDs and NORs for bonus practice.
Edge Triggered D Flip Flop
This is an advanced topic for this course, and I do not expect every student to become familiar with the working of an edge triggered flip flop. The purpose of this exercise is to get a better understanding of this particular black box.
Create a timing diagram for this element: http://en.wikipedia.org/wiki/Flip-flop_(electronics)#Classical_positive-edge-triggered_D_flip-flop
Show a transition from 0 to 1, 1 to 0, 0 to 0, 1 to 1.
This simulator might help: http://www.falstad.com/circuit/e-edgedff.html
Write your own written description of how the flip flop operates, and use it to teach a friend (COOL PARTY TRICK!!). Then, post that description here.