`timescale 1 ps / 100 fs

// If the verilog file containing your register file is
// not named "alu.v" then you will have to change
// to next line as appropriate.
`include "alu.v"

module ALUStimulus();

parameter ClockDelay = 100000;

reg [31:0] BussA, BussB;
reg [1:0] ALUControl;

wire [31:0] Output;
wire zero, overflow,CarryOut;

integer i;

// If your register file module is not named "alu" then you will
// have to change the following line in order to create an instance of
// your register file.  Also you must make sure that the port declarations
// match up with the module instance in this stimulus file.
alu alu1(Output, CarryOut, zero, overflow, BussA, BussB, ALUControl);

initial
    begin
        $monitor($time, " Output=%h, CarryOut=%b, BussA=%h, BussB=%h, ALUControl=%b, Zero=%b, Overflow=%b",
        Output, CarryOut, BussA, BussB, ALUControl, zero, overflow);

    /* Addition unit testing */
        ALUControl=00; 
        BussA=32'hDEF; BussB=32'hABC; // Should output 18AB
        #(ClockDelay);
        BussA=32'h1234; BussB=32'h0105; // Should output 1339
        #(ClockDelay);
        BussA=32'hFFFFFFFF; BussB=32'h00000001; // Should output 0000
        #(ClockDelay);

    /* Subtraction unit testing */
        ALUControl=01; 
        BussA=32'hDEF; BussB=32'hABC; // Should output 333
        #(ClockDelay);
        BussA=32'h1234; BussB=32'h0105; // Should output 112F
        #(ClockDelay);
        BussA=32'h0000; BussB=32'h0001; // Should output FFFF
        #(ClockDelay);

    /* You should test your units EXTENSIVELY here.
           We just gave a few ideas above to get you started.
           Make sure you've checked all outputs for all
           "interesting" cases. */

    end
endmodule