- Last revision: September 11, 2007
- Cadence version at Olin: Cadence IUS 05.40-s021
Basically, follow the instructions at Fall 2007/Installing Cadence.
Running a Verilog Simulation
Previous versions of this tutorial had you using the NClaunch tool, which is a graphical interface to the ncverilog command line simulator. Since NClaunch sucks, we will stick with the command line version.
First, you must put all your Verilog files in a directory that contains no space. Yes, it is 2007, and we still can't deal with spaces. Oh well.
- The command line to do a text-based simulation is:
- The command to utilize the graphical waveform viewer (nice):
ncverilog +access+rwc +gui <filename>
SimVision is a tool that lets you interact, graphically, with waveforms representing the wires in your circuit.
- The default window layout consists of a Design Browser window:
- and a console window:
- In the Design Browser window, you will see a hierarchical representation of your module in the left pane. Clicking on the first (highest-level) module will display all the signals at that hierarchy level in the right pane:
- To add all these signals to the waveform viewer, click on the “Send To: Waveform window” button:
- This will open the Waveform viewer that looks like the screenshot below. To run your simulation, click the Play button.
- The Play button runs your simulation to the $finish statement. It could take some time. Keep an eye on your processor load. When it is finished, you should see traces for all the signals that you selected to probe:
- The signal window will just be zoomed in at the very beginning, and likely you’ll want to zoom out. To zoom out to see everything, click on the magnifying glass with an equals sign in it.
- To add signal probes into lower levels of hierarchy, simply click on the arrow that looks like:
. This opens a pane with the module hierarchy.
- Here you can select modules down in the hierarchy, and pick signals to watch. When you click on signals in the lower left-hand pane, they immediately go to the waveform window.
- Unfortunately, these signals were probably not monitored during the initial simulation. You must reset the simulation and re-run it to collect these values. To do that, simply click on the rewind button next to the play button, and then begin the simulation again.
If you make a change to your design, you will need to reinvoke the simulator. To do so, select Simulation > Reinvoke Simulator. This should re-compile the dependent code you changed, re-elaborate the necessary modules, and reinvoke the simulator on the new snapshot.
- If you ask the simulator to simulate a lot of low-level signals, it will take forever. Your CPU will hit 100% utilization, and the simulation will seem to lock up. In those cases, I have usually just forcibly quit the application from the Windows Task Manager and restarted the simulation with a more selective set of signals.
- Sometimes reinvoking the simulator does not work right. It has thrown various errors when it doesn’t work, none of which seem logical. If all else fails, I simply start over.
- Often, processes will start that lock the design directory even after all Cadence programs seem to be closed. Most likely there is a process oBserver.exe running that needs to be killed to free the directory lock.
- You must be connected to the Olin network in order to use the Cadence simulation tools. The license server is a network machine (STUAPP) and must be reachable. This works reliably over VPN